| Tue, 22 Aug 2023 06:29:27 +0000 |
Mychaela Falconia |
sw/Makefile: add
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| Tue, 22 Aug 2023 06:16:44 +0000 |
Mychaela Falconia |
sw: simtrace3-sniff-rx program written, compiles
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| Tue, 22 Aug 2023 02:44:23 +0000 |
Mychaela Falconia |
sw/libserial: based on FC host tools version
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| Mon, 21 Aug 2023 20:14:26 +0000 |
Mychaela Falconia |
doc: on later thought, drop the DUS term in favor of ME/ID
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| Mon, 21 Aug 2023 19:26:24 +0000 |
Mychaela Falconia |
FPGA make clean: rm *.rpt too
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| Mon, 21 Aug 2023 19:25:35 +0000 |
Mychaela Falconia |
FPGA build: include yosys-wrap in this repository
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| Mon, 21 Aug 2023 06:50:55 +0000 |
Mychaela Falconia |
doc/Sniffer-FPGA-design: update for first implementation
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| Mon, 21 Aug 2023 03:09:34 +0000 |
Mychaela Falconia |
.hgignore: add mv-sniffer gerber files
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| Mon, 21 Aug 2023 03:03:41 +0000 |
Mychaela Falconia |
boards/mv-sniffer/pcb: add Makefile
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| Mon, 21 Aug 2023 03:02:01 +0000 |
Mychaela Falconia |
boards/mv-sniffer: PCB layout done
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| Mon, 21 Aug 2023 01:12:16 +0000 |
Mychaela Falconia |
FPGA Makefile: generate timing.rpt
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| Mon, 21 Aug 2023 01:10:23 +0000 |
Mychaela Falconia |
FPGA Makefile: generate pnr.rpt
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| Mon, 21 Aug 2023 01:07:26 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
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| Mon, 21 Aug 2023 01:05:25 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/sniff_rx.v: typo in signal name
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| Mon, 21 Aug 2023 01:00:16 +0000 |
Mychaela Falconia |
FPGA Makefile: capture yosys stdout
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| Mon, 21 Aug 2023 00:55:33 +0000 |
Mychaela Falconia |
FPGA Makefile: yosys-wrap installed on Mother's system
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