| Tue, 22 Aug 2023 08:55:33 +0000 |
Mychaela Falconia |
doc/PPS-catcher-FSM: initial description
|
| Tue, 22 Aug 2023 06:29:27 +0000 |
Mychaela Falconia |
sw/Makefile: add
|
| Tue, 22 Aug 2023 06:16:44 +0000 |
Mychaela Falconia |
sw: simtrace3-sniff-rx program written, compiles
|
| Tue, 22 Aug 2023 02:44:23 +0000 |
Mychaela Falconia |
sw/libserial: based on FC host tools version
|
| Mon, 21 Aug 2023 20:14:26 +0000 |
Mychaela Falconia |
doc: on later thought, drop the DUS term in favor of ME/ID
|
| Mon, 21 Aug 2023 19:26:24 +0000 |
Mychaela Falconia |
FPGA make clean: rm *.rpt too
|
| Mon, 21 Aug 2023 19:25:35 +0000 |
Mychaela Falconia |
FPGA build: include yosys-wrap in this repository
|
| Mon, 21 Aug 2023 06:50:55 +0000 |
Mychaela Falconia |
doc/Sniffer-FPGA-design: update for first implementation
|
| Mon, 21 Aug 2023 03:09:34 +0000 |
Mychaela Falconia |
.hgignore: add mv-sniffer gerber files
|
| Mon, 21 Aug 2023 03:03:41 +0000 |
Mychaela Falconia |
boards/mv-sniffer/pcb: add Makefile
|
| Mon, 21 Aug 2023 03:02:01 +0000 |
Mychaela Falconia |
boards/mv-sniffer: PCB layout done
|
| Mon, 21 Aug 2023 01:12:16 +0000 |
Mychaela Falconia |
FPGA Makefile: generate timing.rpt
|
| Mon, 21 Aug 2023 01:10:23 +0000 |
Mychaela Falconia |
FPGA Makefile: generate pnr.rpt
|
| Mon, 21 Aug 2023 01:07:26 +0000 |
Mychaela Falconia |
fpga/sniffer-basic/top.v: correct SIM_RST polarity for LED
|
