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annotate lunalcd2/src/vsrc/MAX1916.v @ 70:000411b39576

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lunalcd2/src/Makefile: generate BOM outputs
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 26 Jun 2021 21:16:48 +0000
parents d5d14b426faa
children
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d5d14b426faa lunalcd2: structural Verilog source captured
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1 module MAX1916 (GND, EN, SET, LEDK);
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2
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3 input GND, EN, SET;
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4 output [1:3] LEDK;
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5
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6 /* instantiate the package; the mapping of signals to pins is defined here */
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7
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8 pkg_SOT23_6 pkg (.pin_1(EN),
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9 .pin_2(GND),
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10 .pin_3(SET),
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11 .pin_4(LEDK[3]),
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12 .pin_5(LEDK[2]),
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13 .pin_6(LEDK[1])
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14 );
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15
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16 endmodule