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annotate duart28/src/vsrc/USB_block.v @ 33:0073141010a2

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duart28/src/Makefile: netlist MCL binding added
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Jul 2020 00:10:45 +0000
parents 22aba3a61a4b
children
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1 /*
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2 * This module encapsulates the USB connector, the FT2232D block and
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3 * the glue components between them.
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4 */
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5
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6 module USB_block (GND, P_5V, VCCIOA, VCCIOB,
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7 ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB, PWREN);
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8
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9 output GND, P_5V;
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10
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11 input VCCIOA, VCCIOB;
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12 inout [7:0] ADBUS, BDBUS;
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13 inout [3:0] ACBUS, BCBUS;
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14 input SI_WUA, SI_WUB;
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15 output PWREN;
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16
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17 /* interconnecting wires */
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18
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19 wire VBUS;
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20 wire DM_connector_side, DM_chip_side;
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21 wire DP_connector_side, DP_chip_side;
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22 wire RSTOUT;
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23
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24 usb_conn conn (.GND(GND),
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25 .VBUS(VBUS),
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26 .Dminus(DM_connector_side),
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27 .Dplus(DP_connector_side),
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28 .ID() /* no connect */
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29 );
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30
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31 /* ferrite bead on the power supply */
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32
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33 inductor VBUS_ferrite (VBUS, P_5V);
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34
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35 /* series resistors on USB data lines */
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36
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37 resistor DM_series_R (DM_connector_side, DM_chip_side);
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38 resistor DP_series_R (DP_connector_side, DP_chip_side);
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39
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40 /* we can now bring in the FT2232D block */
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41
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42 FT2232D_block FT2232D (.GND(GND),
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43 .VCC(P_5V),
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44 .VCCIOA(VCCIOA),
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45 .VCCIOB(VCCIOB),
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46 .USBDP(DP_chip_side),
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47 .USBDM(DM_chip_side),
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48 .RESET(P_5V),
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49 .RSTOUT(RSTOUT),
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50 .PWREN(PWREN),
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51 .ADBUS(ADBUS),
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52 .ACBUS(ACBUS),
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53 .SI_WUA(SI_WUA),
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54 .BDBUS(BDBUS),
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55 .BCBUS(BCBUS),
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56 .SI_WUB(SI_WUB)
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57 );
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58
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59 resistor DP_pullup_R (DP_chip_side, RSTOUT);
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60
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61 /* power bypass caps */
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62
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63 capacitor VBUS_in_cap (VBUS, GND);
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64 capacitor P_5V_cap (P_5V, GND);
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65 capacitor P_5V_cap2 (P_5V, GND);
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66
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67 endmodule