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annotate duart28/src/vsrc/regulator_with_caps.v @ 33:0073141010a2

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duart28/src/Makefile: netlist MCL binding added
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Jul 2020 00:10:45 +0000
parents 22aba3a61a4b
children
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Mychaela Falconia <falcon@freecalypso.org>
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1 module regulator_with_caps (GND, IN, OUT);
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2
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3 input GND, IN;
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4 output OUT;
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5
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6 regulator_ic reg (.IN(IN),
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7 .OUT(OUT),
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8 .GND(GND),
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9 .EN(IN)
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10 );
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11
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12 capacitor input_cap (IN, GND);
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13 capacitor output_cap (OUT, GND);
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14
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15 endmodule