FreeCalypso > hg > fc-small-hw
annotate fc-uja/design-spec @ 33:0073141010a2
duart28/src/Makefile: netlist MCL binding added
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 05 Jul 2020 00:10:45 +0000 |
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1 FreeCalypso UART+JTAG Adapter |
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2 Board design specification |
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3 |
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4 1. Purpose and scope |
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5 |
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6 The circuit board described in this specification will be an adapter for |
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7 connecting a host PC or laptop (via USB) to the following 3 development |
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8 interfaces on FreeCalypso GSM devices: |
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9 |
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10 * A 3-wire UART interface intended for RVTMUX on Calypso's IrDA UART |
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11 * Calypso JTAG |
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12 * Iota nTESTRESET |
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13 |
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14 The core function of interfacing from USB to a UART, JTAG and GPIO will be |
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15 performed by an FT2232D chip, but the board described herein has two key |
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16 differences from a generic FT2232x board, key differences which necessitate the |
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17 development of a custom board: |
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18 |
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19 * Our board will have 3-state buffers on the JTAG lines and an open drain |
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20 driver on the nTESTRESET line, wired in such a way that they cannot be |
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21 accidentally turned on while the FT2232D is in its power-up default UART |
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22 mode, prior to the software switch into the MPSSE+GPIO mode. |
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23 |
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24 * The target connection interface will be presented not only on general-purpose |
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25 headers, but also on a special FFC connector, to be used with our future |
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26 FreeCalypso handset boards that will use the FFC-based development interface |
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27 copied from Foxconn's Pirelli DP-L10 phone. |
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28 |
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29 The gadget to be built is intended to serve the following two purposes, in this |
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30 order of importance: |
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31 |
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32 Application 1: the present adapter will be required to do initial bring-up, |
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33 deep development and production-time programming and testing on our upcoming |
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34 FreeCalypso handset boards. Calypso's MODEM UART will be wired to the handset's |
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35 built-in USB-serial port also acting as the charging power source, but that |
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36 interface is intended for end users - deep development, initial bring-up and |
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37 production processes will need to be done through the IrDA UART wired to the |
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38 FFC interface through the present adapter. JTAG is not expected to be needed, |
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39 but is "thrown in for free" - however, the Iota nTESTRESET line will be very |
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40 useful for commanding system switch-on that can be distinguished from both the |
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41 end user power-on button and the charger plug event, as well as for easy |
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42 recovery from any hung state. |
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43 |
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44 Application 2: it costs us nothing extra to bring the target connection |
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45 interface out on generic headers in addition to the FFC connector. If anyone |
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46 needs to play with JTAG on our FCDEV3B or on a Motorola C1xx phone hacked up |
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47 with little wires, the present adapter will be more robust compared to |
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48 unbuffered COTS FT2232x breakout boards thanks to our 3-state buffers |
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49 protecting the JTAG lines from FT2232's initial UART mode garbage. |
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50 |
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51 However, the present FreeCalypso UART+JTAG adapter board is NOT intended to be |
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52 used as a generic JTAG adapter for non-Calypso targets. The set of additional |
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53 signals needed besides JTAG is quite different between the two: most traditional |
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54 (non-GSM) ARM processors and DSPs have TRST and/or SRST signals, and sometimes |
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55 also DBGRQ/DBGACK - whereas the Calypso+Iota chipset has no TRST, and the way |
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56 Iota's nTESTRESET signal works is quite different. Companies like Tin Can Tools |
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57 (Flyswatter2) already provide superb-quality and very cheap FT2232x-based JTAG |
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58 adapters for "generic" applications, and there is no point in trying to compete |
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59 with them - instead we need a Calypso-specific adapter that provides a UART, |
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60 nTESTRESET control and JTAG in this order of priority. |
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61 |
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62 2. Detailed design |
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63 |
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64 2.1. FT2232D core block |
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65 |
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66 The FTDI chip chosen for this adapter board is FT2232D. One of the FT2232x |
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67 devices is needed because we need MPSSE for JTAG plus a second channel for the |
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68 RVTMUX UART, leaving FT2232C/D/L and FT2232H as the two viable candidates. The |
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69 FT2232H high speed device does not offer anything useful for our application, |
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70 hence the more basic FT2232D has been chosen on the principle of "bez nadobnosti |
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71 nosimyj nabryushnik vreden" (a Russian proverb) - introducing USB high speed |
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72 capability (480 Mbps USB signaling) with FT2232H would increase the chances of |
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73 USB signal integrity problems due to suboptimal PCB layout or suboptimal USB |
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74 cable quality while providing absolutely no useful gain in our application, |
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75 whereas FT2232D is inherently safer in this regard by not having that USB high |
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76 speed capability in the first place. FT2232D is a direct drop-in for the |
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77 earlier FT2232C and FT2232L chips; FT2232D is a currently active part available |
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78 from Digi-Key whereas its predecessors are surplus-only parts. |
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79 |
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80 FT2232C/D devices only support MPSSE on Channel A, hence our FreeCalypso |
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81 UART+JTAG adapter will follow the general canon for such adapters in that JTAG |
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82 and test reset will be on Channel A, whereas Channel B will be used for the |
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83 RVTMUX UART. |
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84 |
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85 There will be a 93C46 EEPROM connected to the FT2232D chip. This EEPROM is |
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86 needed so that we can give our adapter a custom USB ID (out of the range of USB |
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87 IDs allocated by FTDI to Falconia Partners LLC); this custom USB ID is needed |
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88 for several reasons: |
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89 |
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90 * We don't want the ftdi_sio driver in the Linux kernel to create two ttyUSBx |
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91 devices for both FT2232D channels only to have the first of the pair disappear |
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92 when a custom libftdi-based program is run to make use of JTAG and/or reset |
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93 functions on Channel A - instead we would like to have this driver create |
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94 only one ttyUSBx device for the UART on Channel B. There already exist |
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95 several other UART+JTAG adapters whose creators and users had the same need, |
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96 and the ftdi_sio driver in Linux supports them. The existing adapters of |
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97 this kind are identified by custom USB IDs, and once our own adapter advances |
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98 past the vaporware phase, we'll be submitting a one-line patch to the Linux |
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99 kernel driver to add our custom USB ID to the list. |
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100 |
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101 * We will have a custom libftdi-based program for sending nTESTRESET to the |
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102 FreeCalypso GSM device target through our adapter; this program will have an |
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103 easier time locating our USB device among other potential FTDI-based devices |
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104 if we use a custom USB ID. |
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105 |
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106 * When the time comes to configure OpenOCD to do JTAG through our adapter, |
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107 having a custom USB ID will similarly help prevent erroneous binding to other |
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108 FTDI-based devices that may be present. |
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109 |
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110 2.2. Buffering logic for JTAG |
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111 |
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112 One significant design blemish of the otherwise quite versatile FT2232D is that |
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113 "bit" modes like MPSSE cannot be configured in the EEPROM, instead they can only |
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114 be entered dynamically on software command from the host. As the result, an |
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115 FT2232D channel that is meant to be used for, say, JTAG on a given board will |
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116 still operate in its default UART mode when USB power is first applied, and will |
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117 remain in this state indefinitely long, until the user runs a program on the |
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118 host that issues a software command to enter the "bit" mode - which may never |
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119 happen. If an FT2232D channel is wired for JTAG but the chip operates in its |
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120 default UART mode, the following problems will occur if the signals are wired |
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121 directly without additional buffering logic: |
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122 |
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123 * The ADBUS0 line which becomes TCK in JTAG mode is TxD in UART mode, and will |
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124 thus drive a high level on power-up - even though the quiescent state on TCK |
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125 should be low. |
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126 |
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127 * JTAG TDO line (output from the target) needs to be connected to ADBUS2 - this |
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128 signal becomes an input in MPSSE mode - but in the power-up default UART mode |
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129 ADBUS2 is an output. Thus this default output can end up fighting with the |
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130 target's TDO output, potentially damaging the target, the adapter or both. |
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131 |
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132 (The other two JTAG signals - TDI and TMS driven from ADBUS1 and ADBUS3 - are |
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133 less of a problem because in the power-up default UART mode these FT2232D pins |
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134 are inputs with weak internal pull-ups on them.) |
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135 |
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136 Our solution to this problem is to insert 3-state buffers (unidirectional in |
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137 the JTAG signal direction) into all 4 JTAG lines. We shall use 3-state buffers |
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138 with active-low enables, and the two enable lines (one for the TCK, TDI and TMS |
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139 outputs from the adapter, the other for the TDO input) will come from FT2232D |
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140 pins ADBUS5 and ADBUS6. In the MPSSE mode used for JTAG these pins become GPIOs |
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141 and will need to be configured as outputs driving low in order to enable JTAG, |
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142 but in the power-up default UART mode they are inputs with internal pull-ups, |
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143 and we will have additional external pull-ups for safety. The effects will be |
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144 as follows: |
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145 |
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146 * As long as the FT2232D channel is in UART mode, the 3-state buffers can never |
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147 be enabled. All JTAG outputs from the adapter will be tristated (i.e., the |
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148 same as if the adapter weren't there, presenting the target with its normal |
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149 sans-JTAG state), there will be no fighting on ADBUS2, and the UART will sense |
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150 all of its inputs as inactive high. |
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151 |
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152 * As the MPSSE mode is entered on software command, the initial pin direction |
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153 mask byte should be 0x01, keeping ADBUS0 as an output, but then an MPSSE GPIO |
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154 command should be given, enabling the other outputs along with sensible |
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155 initial values. |
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156 |
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157 * ADBUS6 should be driven low to enable the TDO receiving buffer (it will have |
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158 a weak pull-up on the buffer's input in order to not float when there is no |
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159 target connected) right after ADBUS2 is switched to being an input, but |
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160 ADBUS5 can be driven low or high at any time afterward to enable or disable |
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161 the JTAG outputs. |
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162 |
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163 2.3. Sideband signals alongside JTAG |
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164 |
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165 2.3.1. Iota nTESTRESET driver |
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166 |
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167 The test reset line in the Calypso+Iota solution (nTESTRESET) is handled by the |
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168 VRPC block in the Iota ABB which is essentially a PMIC. It is always pulled up |
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169 inside the GSM device to a non-logic power rail, and this circuit works even |
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170 when the mobile is in the switched-off state with all of the main voltage |
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171 regulators for regular logic turned off. The raw nTESTRESET line is not meant |
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172 to ever be driven by any kind of active push-pull logic driver; instead it is |
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173 meant to be shorted to GND to trigger the reset, through either a pushbutton |
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174 switch or an OC/OD driver. |
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175 |
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176 Back when TI made their x-Sample and Leonardo development boards, they |
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177 apparently preferred to drive their JTAG+reset test interface (14-pin header in |
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178 TI's JTAG pinout) with whatever generic (non-Calypso-specific) JTAG adapter |
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179 they already had at the time, and as their 14-pin JTAG interface was defined, |
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180 pin 2 (reset) was defined to be TRST with an active push-pull driver in the |
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181 JTAG host adapter (or "emulator" as they call it). These x-Sample and Leonardo |
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182 boards have a little on-board circuit between this connector pin 2 and the |
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183 actual nTESTRESET; this circuit consists of two transistors and has the effect |
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184 of protecting the internal nTESTRESET line from whatever the external driver |
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185 may be doing: if the external adapter drives a logic low, the transistor circuit |
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186 pulls nTESTRESET low via what is effectively an OC driver, otherwise the JTAG |
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187 block presents a Hi-Z state to the nTESTRESET line. This circuit has been |
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188 copied from Leonardo schematics on our own FCDEV3B, but the current plan is to |
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189 not include it on the handset board, instead bringing out nTESTRESET in its |
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190 native form on the FFC interface like the Pirelli DP-L10 board appears to do. |
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191 |
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192 Our FreeCalypso UART+JTAG adapter will drive this nTESTRESET pin with an open |
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193 drain driver. This driving arrangement is compatible with both approaches: |
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194 either direct nTESTRESET connection or the transistor circuit on FCDEV3B and on |
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195 TI's boards. It does, however, make our adapter specific to Calypso+Iota GSM |
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196 devices: more generic ARM processors and DSPs will often have more standard |
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197 TRST and/or SRST signals instead, possibly needing active push-pull drivers. |
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198 |
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199 To protect the reset line from FTDI's UART-default bogosity, the input to the |
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200 non-inverting open drain driver will come from ADBUS7, which is an input in the |
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201 FT2232D's power-up default UART mode. Like ADBUS5 and ADBUS6 controls for the |
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202 3-state buffers for JTAG, this ADBUS7 line will have an additional external |
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203 pull-up for safety, thus the reset can never be triggered accidentally while |
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204 the FT2232D channel is in UART mode - the only way to trigger the test reset |
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205 will be to first put the channel into the MPSSE+GPIO mode, then make ADBUS7 an |
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206 output driving low. |
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207 |
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208 2.3.2. Calypso nEMU0 and nEMU1 pins |
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209 |
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210 The Calypso chip has two JTAG-sideband pins called nEMU0 and nEMU1. They form |
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211 some kind of debug/development interface which is not needed in normal product |
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212 operation, and all Calypso-based GSM phone and modem product boards known to us |
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213 leave them unconnected - even those product boards on which the regular JTAG |
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214 pins are brought out (Pirelli DP-L10 and some Mot C1xx variants). TI's |
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215 Leonardo schematics leave them unconnected as well, but their more complete |
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216 x-Sample boards have them brought out to the 14-pin JTAG connector. Our |
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217 FCDEV3B has them brought out as well. |
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218 |
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219 The problem with these nEMU0 and nEMU1 pins is that they are undocumented: the |
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220 docs we have only say that they are bidirectional signals with pull-ups, and |
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221 nothing else. We have on-board pull-ups on these two lines on our FCDEV3B |
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222 (copied from TI's E-Sample board) strengthening the Calypso chip's supposed |
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223 internal pull-ups, but we don't know what will happen if either or both pins |
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224 are driven low externally (at boot or any other time), nor do we know if the |
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225 Calypso chip itself ever drives or pulses them low as outputs. Common sense |
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226 suggests that one of their likely functions is probably to hold the ARM7 core |
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227 in the debug halt state directly out of reset, and possibly disable the |
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228 watchdog timer which is otherwise enabled and ticking at this time - but we |
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229 don't know any of the details. |
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230 |
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231 Because we don't know exactly how these nEMU0 and nEMU1 pins work, the only |
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232 sense in which we can support them is to provide a way to use our FreeCalypso |
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233 UART+JTAG adapter as a reverse engineering tool, experimentally playing with |
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234 these nEMU[1:0] pins on an FCDEV3B. We are going to make the following simple |
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235 provision to facilitate such experimentation: we are going to connect FT2232D |
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236 pins ACBUS2 and ACBUS3 to pins 13 and 14 on the 14-pin JTAG header, which are |
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237 the pins for nEMU0 and nEMU1. Unlike all other signals, this one will be a |
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238 direct connection without any buffering. ACBUS2 and ACBUS3 function as open |
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239 drain LED drivers in the power-up default UART mode, and these pins have been |
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240 chosen on the reasoning that they are expected to stay non-driving as long as |
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241 no one actually opens Channel A as a UART and tries to send something through |
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242 it. The following important additional considerations apply: |
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243 |
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244 * These nEMU0 and nEMU1 signals are NOT included in the FFC interface defined |
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245 by Foxconn/Pirelli which we are copying for our FreeCalypso handset boards. |
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246 The positive implication is that the development interface for these FC |
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247 handset boards will not be adversely affected by the potentially dangerous |
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248 unbuffered connection to FT2232D pins; the negative implication is that if we |
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249 ever do learn how to use these nEMU[1:0] pins to do whatever they can do, |
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250 that ability won't be available on the handset boards. However, the latter |
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251 loss is deemed to be acceptable: the most plausible function of these |
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252 nEMU[1:0] pins is to enter JTAG debug state directly out of reset, and we |
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253 don't need this ability when we have the internal boot ROM enabled via nIBOOT: |
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254 we can interrupt and divert the boot process serially, and then enter the |
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255 debug state through the regular JTAG scan chain. |
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256 |
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257 * Anyone using the 14-pin JTAG header interface to connect to a target such as |
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258 FCDEV3B that does have nEMU0 and nEMU1 signals on pins 13 and 14 still has |
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259 the freedom to connect or not connect these signals as desired. With our |
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260 current FCDEV3B certain mechanical constraints practically impose the |
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261 requirement of making a custom cable in any case: the spacing between headers |
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262 on the FCDEV3B is too tight for standard ribbon cables terminated with IDC |
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263 connectors (there is no room for the bulky sides of those IDC connectors), |
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264 hence one needs to crimp female terminals onto individual wires and insert |
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265 them into a crimp housing instead. In light of these considerations, you |
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266 should only connect pins 13 and 14 between our adapter and your target if you |
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267 are specifically interested in experimenting with driving or sensing Calypso's |
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268 nEMU0 and nEMU1 signals, otherwise leave them unconnected. |
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269 |
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270 * Our entire "support" for these nEMU[1:0] pins will consist of two PCB traces |
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271 connecting FT2232D's ACBUS2 and ACBUS3 pins to two pins on the 14-pin JTAG |
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272 header. This arrangement, which could be considered quite risky under |
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273 different circumstances, does absolutely nothing and cannot cause any harm if |
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274 those two header pins are NOT subsequently connected to an actual Calypso |
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275 target. |
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276 |
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277 2.4. FT2232D I/O pin summary |
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278 |
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279 Channel A pins will be assigned and connected as follows: |
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280 |
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281 ADBUS0: JTAG TCK (fixed by FTDI) |
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282 ADBUS1: JTAG TDI (fixed by FTDI) |
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283 ADBUS2: JTAG TDO (fixed by FTDI) |
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284 ADBUS3: JTAG TMS (fixed by FTDI) |
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285 ADBUS4: unused and unconnected |
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286 ADBUS5: active-low output enable control for JTAG outputs |
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287 ADBUS6: active-low output enable control for TDO receiving buffer |
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288 ADBUS7: active-low nTESTRESET control |
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289 |
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290 ACBUS0: unused and unconnected |
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291 ACBUS1: unused and unconnected |
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292 ACBUS2: wired to JTAG header pin 13 (nEMU0) |
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293 ACBUS3: wired to JTAG header pin 14 (nEMU1) |
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294 |
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295 The 3 pins that are unused and unconnected (ADBUS4, ACBUS0 and ACBUS1) can be |
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296 configured as either inputs with internal pull-ups or outputs. For the |
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297 remaining pins which do have assigned functions, the following software init |
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298 sequence should be adhered to: |
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299 |
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300 * As the MPSSE mode is entered on software command, the initial pin direction |
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301 mask byte should be 0x01. The critical points are to set ADBUS0 as an output |
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302 at this point so it never glitches through a non-driving state (it is TxD in |
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303 the power-up default UART mode), make ADBUS2 an input as it will need to be |
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304 once TDO is enabled, and set ADBUS5-7 as inputs. ADBUS5-7 need to be inputs |
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305 at this stage (the connected logic will sense the inactive high level from |
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306 pull-up resistors) because the initial output value for initialized-as-output |
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307 pins is not defined. |
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308 |
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309 * MPSSE Set Data Bits High Byte (0x82) command should be given to set ACBUS2 |
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310 and ACBUS3 as inputs, leaving nEMU[0:1] pins undisturbed until and unless you |
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311 are playing with them. |
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312 |
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313 * MPSSE Set Data Bits Low Byte (0x80) command should be given to make ADBUS0 |
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314 (TCK) an output driving 0, make ADBUS1 (TDI) an output driving 1, keep ADBUS2 |
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315 as an input from the MPSSE mode entry step, make ADBUS3 (TMS) an output |
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316 driving 1, and make ADBUS6 (TDO receiving buffer control) an output driving 0. |
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317 ADBUS5 (JTAG output buffer control) and ADBUS7 (nTESTRESET driver) should be |
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318 configured as outputs at this point, but their driving values will depend on |
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319 the application. |
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320 |
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321 Channel B will be used as a data-leads-only UART with standard wiring requiring |
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322 no software intervention: |
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323 |
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324 BDBUS0: TxD (UART output) |
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325 BDBUS1: RxD (UART input) |
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326 the rest: unused and unconnected |
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327 |
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328 2.5. Logic voltage levels and buffering |
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329 |
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330 Many FT2232x-based JTAG adapters have level-translating buffers between FT2232x |
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331 pins and the target interface in order to support targets with different logic |
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332 voltage levels, usually from 3.3 V down to 1.8 V, or sometimes an even wider |
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333 allowed range: for example, the Flyswatter2 adapter from Tin Can Tools supports |
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334 target logic voltage levels from 1.6 to 5.0 V. |
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335 |
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336 In our case such voltage level shifting is not really needed: Calypso is 2.8 V |
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337 native, but perfectly tolerant of 3.3 V inputs as well. The following |
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338 approaches have been considered for our FreeCalypso UART+JTAG adapter: |
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339 |
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340 Approach 1: put a 3.3 V regulator on our board, run FT2232D I/O pins at 3.3 V, |
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341 run the 3-state buffers for JTAG at 3.3 V as well, and connect the UART lines |
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342 to FT2232D Channel B pins directly, without buffering. This approach relies on |
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343 Calypso's inputs being tolerant of 3.3 V and Calypso's 2.8 V outputs producing |
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344 voltage levels suitable for 3.3 V inputs. In practice this approach has already |
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345 been used quite extensively in other contexts: we connect Calypso I/O to 3.3 V |
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346 logic when we connect FCDEV3B UARTs to generic off-the-shelf FT2232x adapter |
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347 boards, users of headset jack serial adapters for Motorola and Openmoko phones |
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348 do likewise, Openmoko connected Calypso's 2.8 V UART to their 3.3 V application |
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349 processor, and Foxconn/Pirelli appear to have done likewise with their built-in |
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350 USB-serial interface based on a CP2102 chip with 3.3 V I/O. |
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351 |
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352 Approach 2: put both 3.3 V and 2.8 V regulators on our board, run FT2232D I/O |
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353 pins at 3.3 V (the lowest I/O voltage officially supported by FT2232x chips), |
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354 have the inputs from the Calypso target go directly to 3.3 V logic like with |
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355 Approach 1, but run the 3-state buffers for JTAG outputs plus an always-enabled |
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356 buffer for the UART output at 2.8 V. This approach makes the adapter's outputs |
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357 2.8 V proper, but at the cost of an extra on-board regulator. |
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358 |
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359 Approach 3: similar to Approach 2, but omit the on-board 2.8 V regulator and |
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360 instead power the 2.8 V output buffers from the target voltage reference pin |
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361 provided both on TI's 14-pin JTAG interface (used on development boards, both |
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362 TI's and our own FCDEV3B) and on the FFC interface we are copying from |
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363 Foxconn/Pirelli. Compared to Approach 2, this approach eliminates the extra |
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364 on-board regulator, but would cause some power to be drawn from the target to |
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365 power the output buffers. This approach would also create difficulties if a |
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366 user wishes to use the generic header interface (as opposed to the highly |
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367 specialized FFC interface), and there is no source from which the target |
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368 reference voltage pin can be supplied. A compromise approach could be |
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369 implemented by putting a 3-pin jumper header on our board, selecting the power |
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370 to the output buffers between internal 3.3 V and the external target voltage |
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371 reference pin, but having that jumper set to the internal 3.3 V supply would |
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372 effectively bring us back to Approach 1. |
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373 |
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374 Approach 4: do what the "big guys" do in terms of voltage level translation: |
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375 use special dual-supply translating buffers in both directions, supporting any |
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376 target voltage level at least between 1.8 and 3.3 V or possibly wider. This |
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377 approach would be appropriate for a more general-purpose JTAG adapter that needs |
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378 to work with, say, 1.8 V targets, but given that our adapter is specific to the |
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379 Calypso which has 2.8V-native, 3.3V-tolerant I/O, the extra complexity of |
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380 full-blown voltage level translation is not really justifiable. |
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381 |
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382 Approaches 3 and 4 are excessively complex and cumbersome, and cannot be |
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383 justified in our Calypso-specific application. The practical choice is thus |
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384 between approaches 1 and 2. My (Mother Mychaela's) initial leaning was toward |
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385 Approach 1, but upon further reflection I swayed over to Approach 2. The cost |
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386 of the additional on-board 2.8 V regulator in terms of PCB real estate and |
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387 layout complexity is not too great, and given that our adapter is very |
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388 specifically for the Calypso and no other targets, it makes more sense to put |
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389 out Calypso's native voltage levels, rather than merely compatible ones. |
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390 |
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391 Approach 2 will be used on our FreeCalypso UART+JTAG adapter, with the following |
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392 additional nuances: |
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393 |
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394 * A 74LVC125A output buffer (4 individual buffers in one package) powered from |
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395 the 2.8 V regulator will be used for the 4 logic outputs from our adapter: |
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396 JTAG outputs TCK, TDI and TMS, and the single UART output. The output enables |
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397 for the JTAG outputs will come from ADBUS5, whereas the UART output will be |
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398 always enabled. |
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399 |
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400 * Another similar buffer, but powered from the 3.3 V regulator will be used for |
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401 the two logic signals going the other way: JTAG TDO and the UART input. The |
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402 buffer for TDO will be enabled by ADBUS6, the UART input will be always |
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403 enabled. There will be a pull-up resistor to local 2.8 V on the input |
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404 (target interface) side of each buffer. The buffer for TDO is needed for |
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405 3-state control, but an identical buffer will also be used for the UART input |
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406 for the sake of symmetry, and to present the target with a pull-up to 2.8 V |
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407 rather than FT2232D's internal pull-up to 3.3 V. |
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408 |
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409 * All pull-ups on the interface between FT2232D pins and the just-described |
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410 buffers will be to 3.3 V. |
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411 |
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412 * A dedicated 3.3 V regulator will be used, instead of trying to use the feeble |
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413 one built into the FT2232D, as the datasheet-stated limit of 5 mA seems like |
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414 too little margin. |
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415 |
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416 * The only interface on which the target would ever see 3.3 V rather than 2.8 V |
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417 will be the purely experimental provision for Calypso nEMU[1:0] described in |
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418 section 2.3.2, to be used only by those who are specifically interested in |
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419 that line of experimentation, and not in any other use cases. It makes no |
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420 sense to attempt voltage level-translating buffering for these signals when |
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421 we don't even know if they are really inputs or outputs, and under what |
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422 conditions. |
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423 |
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424 The target voltage reference pins on the TI-style 14-pin JTAG header connector |
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425 and on the Foxconn/Pirelli-style FFC connector will remain unused and |
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426 unconnected. One could make an argument that not using the target-provided I/O |
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427 voltage reference is wrong, but the issue needs to be seen in context. TI's |
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428 14-pin JTAG interface was designed for use in a wide range of applications, |
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429 covering I/O voltages at least between 1.8 and 3.3 V, and TI's XDS JTAG adapters |
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430 support this wide range of I/O voltages just like the ones made by community |
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431 vendors like Amontec and Tin Can Tools. In the case of Foxconn and their |
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432 Pirelli DP-L10 design, we can never know for certain, but it is highly plausible |
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433 that they weren't making a custom FT2232x-based JTAG adapter of their own like |
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434 we are doing, and instead had a passive adapter that connected their FFC |
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435 interface to some existing TI XDS JTAG adapter, likely via that very same 14-pin |
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436 interface. In that case the existing TI XDS JTAG adapter they were using needed |
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437 a target voltage reference pin, and so they included one in their custom FFC |
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438 interface. But our circumstances are different: we are making a custom |
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439 UART+JTAG adapter for reasons of our own, and because our custom adapter is |
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440 very specific to the Calypso, having our own on-board 2.8 V regulator is more |
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441 robust than depending on an I/O buffer supply from the target. |
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442 |
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443 2.6. Target connection interfaces |
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444 |
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445 2.6.1. Generic header interface |
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446 |
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447 Our FreeCalypso UART+JTAG adapter will feature two header connectors: a 14-pin |
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448 header in TI's pinout for JTAG, nEMU[1:0] and nTESTRESET, and a separate 3-pin |
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449 header for the UART. This header interface option will make it possible to use |
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450 our adapter with the FCDEV3B, with TI's D-Sample board (JTAG+company 14-pin |
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451 interface only) and even with hacked-up C1xx phones with little wires soldered |
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452 to JTAG test pads. As explained in section 2.3.2, always give explicit thought |
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453 as to whether pins 13 and 14 (nEMU0 and nEMU1) should be connected or not in |
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454 your application. |
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455 |
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456 The UART on FT2232D Channel B will be completely independent of JTAG and other |
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457 Channel A functions, and can be used as a completely generic data-leads-only |
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458 asynchronous serial interface at 2.8 V. |
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459 |
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460 2.6.2. FFC interface |
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461 |
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462 Our upcoming FreeCalypso handset boards will need to use an FFC interface for |
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463 development functions. At the very minimum this interface needs to connect the |
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464 Calypso's IrDA UART carrying RVTMUX, and do it in such a way that this serial |
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465 interface can be connected without applying a "charger present" condition to |
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466 the VRPC block in the Iota ABB - hence the need for an interface outside of the |
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467 handset's built-in USB-serial port. Furthermore, if we copy the FFC interface |
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468 from Foxconn's Pirelli DP-L10 design instead of inventing our own, we get not |
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469 only a UART channel, but also JTAG and nTESTRESET on the same interface. There |
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470 is very little need for JTAG in FreeCalypso, but it is certainly a nice-to-have. |
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471 Having the ability to drive nTESTRESET from the development host will also come |
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472 very useful: once we implement proper handset on/off logic in the firmware, |
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473 meaning that different switch-on causes will be treated like they should be in |
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474 a real handset, switch-on from nTESTRESET will become the development and |
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475 production boot mode. |
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476 |
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477 Our FFC interface is effectively defined by the unpopulated FFC connector |
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478 footprint and its wiring found in Pirelli DP-L10 phones. It is a 12-pin FFC |
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479 interface with 0.5 mm pitch, the unpopulated connector footprint on Pirelli's |
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480 PCB has pin numbers marked on the silk screen, and the pins are assigned as |
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481 follows: |
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482 |
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483 Pin Function |
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484 ---------------- |
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485 1 V-IO rail |
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486 2 UART Rx (input to the target) |
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487 3 Iota nTESTRESET |
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488 4 JTAG TDI |
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489 5 JTAG TMS |
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490 6 JTAG TCK |
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491 7 UART Tx (output from the target) |
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492 8 JTAG TDO |
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493 9 unused |
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494 10 GND |
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495 11 unused |
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496 12 unused |
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497 |
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498 At one time we had a plan to add Calypso nEMU[1:0] signals to this interface by |
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499 putting them on the last two unused pins, but this addition has been rejected |
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500 for the time being: because we have no documentation for what these nEMU[1:0] |
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501 pins do and all we can do with them are reverse engineering experiments, these |
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502 signals should be kept out of handset products and limited to development boards |
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503 like FCDEV3B for the time being. |
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504 |
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505 There is, however, one critical aspect of this FFC interface which cannot be |
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506 recovered from the Pirelli DP-L10 artifacts and instead has to be defined anew: |
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507 the question of top vs. bottom orientation. Our decision process in this regard |
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508 begins with the availability of FFC jumpers, i.e., the flat flexible piece that |
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509 goes between the two boards. The FFC jumper version with same-side contacts is |
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510 readily available from Digi-Key as very inexpensive single pieces, but the |
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511 version with opposite-side contacts is only available with a prohibitely |
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512 expensive MOQ. Having settled on the FFC jumper with same-side contacts, we |
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513 are left with two options: have the contacts on both sides face upward, or have |
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514 them face downward. The decision between the two is completely arbitrary and |
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515 we have no way of knowing which way Foxconn had it back in their day, but we |
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516 have to decide one way or the other starting with the design of this adapter |
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517 board. The Mother's arbitrary decision is to have the contacts on both sides |
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518 of the FFC jumper face upward, meaning that: |
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519 |
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520 * The FFC connector on the FreeCalypso UART+JTAG Adapter board will need to be |
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521 the top-side contacts version. |
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522 |
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changeset
|
523 * If we are going to populate an FFC connector on a decased Pirelli motherboard |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524 in order to exercise our adapter against that pre-existing target, the top- |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 side contacts version will need to be used. We'll need to do the same if we |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 make our own handset board on which the FFC connector is on the side with the |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 display and the main keypad buttons. |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 * If we make our own handset board on which the FFC connector is on the bottom |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 side of the motherboard (the side opposite the display), which is the current |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531 plan, the connector will need to be the bottom-side contacts version. |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
533 Because pin 1 is on the left on the existing target board with the connector on |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 the top side (Pirelli DP-L10) and we are using the same-side jumper version that |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 flips the left/right orientation, pin 1 will need to be on the right in the |
0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 connector footprint definition on the adapter board. |