annotate mmtb1/schem+bom/primitives @ 8:082bc8d71a42

lunalcd1: updated footprint for LDO regulator
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 01 Apr 2020 21:14:56 +0000
parents 0f9bdd60ce50
children
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Mychaela Falconia <falcon@freecalypso.org>
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1 /*
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2 * This file defines the primitives to be instantiated from the structural
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Mychaela Falconia <falcon@freecalypso.org>
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3 * Verilog source for the board: IC package types, basic components and
0f9bdd60ce50 fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
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4 * subpackages to be mapped later in the MCL binding step.
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5 */
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6
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Mychaela Falconia <falcon@freecalypso.org>
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7 resistor numpins 2;
0f9bdd60ce50 fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
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8 capacitor numpins 2;
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Mychaela Falconia <falcon@freecalypso.org>
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9
0f9bdd60ce50 fc-small-hw separated from old freecalypso-schem repo
Mychaela Falconia <falcon@freecalypso.org>
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10 diode mapped_pins (A, C);
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Mychaela Falconia <falcon@freecalypso.org>
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11 mosfet mapped_pins (G, S, D);
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Mychaela Falconia <falcon@freecalypso.org>
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12
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Mychaela Falconia <falcon@freecalypso.org>
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13 /* connectors */
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Mychaela Falconia <falcon@freecalypso.org>
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14 header_2pin numpins 2;
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Mychaela Falconia <falcon@freecalypso.org>
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15 conn_3pin numpins 3;
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Mychaela Falconia <falcon@freecalypso.org>
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16 header_10pin numpins 10;
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17 conn_40pin_plus2 numpins 42;
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Mychaela Falconia <falcon@freecalypso.org>
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18
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Mychaela Falconia <falcon@freecalypso.org>
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19 /* misc peripherals */
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Mychaela Falconia <falcon@freecalypso.org>
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20 pkg_SIM_socket mapped_pins (C1, C2, C3, C5, C6, C7, M1, M2);
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21 pkg_pushbutton_4pin numpins 4;