FreeCalypso > hg > fc-small-hw

annotate duart28/src/vsrc/board.v @ 23:22aba3a61a4b

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duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
parents
children 9e71844f4db0
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22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
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1 module board ();
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Mychaela Falconia <falcon@freecalypso.org>
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2
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Mychaela Falconia <falcon@freecalypso.org>
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3 wire GND, P_5V, P_3V3, P_2V8;
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Mychaela Falconia <falcon@freecalypso.org>
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4
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5 wire [7:0] ADBUS, BDBUS;
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Mychaela Falconia <falcon@freecalypso.org>
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6 wire [3:0] ACBUS, BCBUS;
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7
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8 USB_block usb ( .GND(GND),
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Mychaela Falconia <falcon@freecalypso.org>
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9 .P_5V(P_5V),
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Mychaela Falconia <falcon@freecalypso.org>
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10 .VCCIOA(P_3V3),
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Mychaela Falconia <falcon@freecalypso.org>
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11 .VCCIOB(P_3V3),
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12 .ADBUS(ADBUS),
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13 .ACBUS(ACBUS),
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Mychaela Falconia <falcon@freecalypso.org>
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14 .SI_WUA(P_3V3),
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Mychaela Falconia <falcon@freecalypso.org>
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15 .BDBUS(BDBUS),
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16 .BCBUS(BCBUS),
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Mychaela Falconia <falcon@freecalypso.org>
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17 .SI_WUB(P_3V3),
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18 .PWREN() /* no connect */
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Mychaela Falconia <falcon@freecalypso.org>
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19 );
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20
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21 regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3));
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Mychaela Falconia <falcon@freecalypso.org>
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22 regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8));
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23
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24 application_block app ( .GND(GND),
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25 .P_2V8(P_2V8),
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26 .ADBUS(ADBUS),
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27 .BDBUS(BDBUS)
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28 );
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29
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30 endmodule