FreeCalypso > hg > fc-small-hw

annotate lunalcd2/src/primitives @ 60:38c713964bb7

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd2: MCL binding complete
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 19:01:35 +0000
parents d5d14b426faa
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
5
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /* passives */
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 resistor numpins 2;
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 capacitor numpins 2;
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
59
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
5 /* LCD module */
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
6 lcd_module_fp numpins 36;
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
7
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
8 /* MAX1916 IC */
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
9 pkg_SOT23_6 numpins 6;
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
10
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
11 /* DIP switch pack */
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
12 pkg_DIP_SW_x4 numpins 8;
5
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 /* connectors */
59
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
15 header_2pin numpins 2;
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents: 5
diff changeset
16 header_26pin numpins 26;