FreeCalypso > hg > fc-small-hw
annotate bb2fc/schem+bom/schem.v @ 20:54e5edfe2f04
duart28 project started
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 13 Jun 2020 05:12:39 +0000 |
parents | 0f9bdd60ce50 |
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rev | line source |
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1 module board (); |
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2 |
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3 wire GND, P_5V, P_1V8, P_2V8; |
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4 wire REGEN; |
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5 |
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6 wire OMAP_McBSP_DR, OMAP_McBSP_FS, OMAP_McBSP_CLK, OMAP_McBSP_DX; |
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7 wire OMAP_UART_RTS, OMAP_UART_RxD, OMAP_UART_TxD, OMAP_UART_CTS; |
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8 |
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9 wire Calypso_MCSI_TXD, Calypso_MCSI_RXD, Calypso_MCSI_CLK, Calypso_MCSI_FSYNCH; |
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10 wire Calypso_UART_TxD, Calypso_UART_RxD, Calypso_UART_RTS, Calypso_UART_CTS; |
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11 |
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12 conn_28pin bb_xm_conn ( .pin_1(P_1V8), |
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13 .pin_2(P_5V), |
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14 .pin_3(), |
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15 .pin_4(OMAP_UART_CTS), |
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16 .pin_5(), |
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17 .pin_6(OMAP_UART_TxD), |
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18 .pin_7(), |
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19 .pin_8(OMAP_UART_RxD), |
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20 .pin_9(), |
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21 .pin_10(OMAP_UART_RTS), |
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22 .pin_11(), |
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23 .pin_12(OMAP_McBSP_DX), |
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24 .pin_13(), |
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25 .pin_14(OMAP_McBSP_CLK), |
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26 .pin_15(), |
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27 .pin_16(OMAP_McBSP_FS), |
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28 .pin_17(), |
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29 .pin_18(OMAP_McBSP_DR), |
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30 .pin_19(), |
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31 .pin_20(), |
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32 .pin_21(), |
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33 .pin_22(), |
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34 .pin_23(), |
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35 .pin_24(), |
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36 .pin_25(REGEN), |
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37 .pin_26(), |
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38 .pin_27(GND), |
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39 .pin_28(GND) |
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40 ); |
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41 |
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42 capacitor C1 (P_5V, GND); |
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43 capacitor C3 (P_1V8, GND); |
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44 |
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45 regulator reg ( .IN(P_5V), |
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46 .OUT(P_2V8), |
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47 .GND(GND), |
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48 .EN(P_5V) |
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49 ); |
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50 |
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51 capacitor C2 (P_2V8, GND); |
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52 |
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53 /* U1 for MCSI */ |
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54 |
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55 buffer_ic_common U1common (.VccA(P_2V8), |
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56 .VccB(P_1V8), |
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57 .GND(GND), |
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58 .OE(GND) |
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59 ); |
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60 |
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61 capacitor C4 (P_2V8, GND); |
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62 capacitor C5 (P_1V8, GND); |
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63 |
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64 buffer_ic_slot U1slot1 (.A(Calypso_MCSI_TXD), |
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65 .B(OMAP_McBSP_DR), |
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66 .DIR(P_2V8) |
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67 ); |
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68 |
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69 buffer_ic_slot U1slot2 (.A(Calypso_MCSI_FSYNCH), |
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70 .B(OMAP_McBSP_FS), |
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71 .DIR(P_2V8) |
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72 ); |
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73 |
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74 buffer_ic_slot U1slot3 (.A(Calypso_MCSI_CLK), |
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75 .B(OMAP_McBSP_CLK), |
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76 .DIR(P_2V8) |
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77 ); |
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78 |
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79 buffer_ic_slot U1slot4 (.A(Calypso_MCSI_RXD), |
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80 .B(OMAP_McBSP_DX), |
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81 .DIR(GND) |
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82 ); |
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83 |
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84 header_5pin J2 (.pin_1(GND), |
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85 .pin_2(Calypso_MCSI_TXD), |
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86 .pin_3(Calypso_MCSI_FSYNCH), |
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87 .pin_4(Calypso_MCSI_CLK), |
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88 .pin_5(Calypso_MCSI_RXD) |
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89 ); |
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90 |
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91 /* U2 for UART */ |
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92 |
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93 buffer_ic_common U2common (.VccA(P_2V8), |
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94 .VccB(P_1V8), |
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95 .GND(GND), |
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96 .OE(GND) |
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97 ); |
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98 |
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99 capacitor C6 (P_2V8, GND); |
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100 capacitor C7 (P_1V8, GND); |
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101 |
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102 buffer_ic_slot U2slot1 (.A(Calypso_UART_CTS), |
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103 .B(OMAP_UART_RTS), |
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104 .DIR(GND) |
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105 ); |
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106 |
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107 buffer_ic_slot U2slot2 (.A(Calypso_UART_TxD), |
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108 .B(OMAP_UART_RxD), |
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109 .DIR(P_2V8) |
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110 ); |
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111 |
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112 buffer_ic_slot U2slot3 (.A(Calypso_UART_RxD), |
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113 .B(OMAP_UART_TxD), |
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114 .DIR(GND) |
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115 ); |
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116 |
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117 buffer_ic_slot U2slot4 (.A(Calypso_UART_RTS), |
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118 .B(OMAP_UART_CTS), |
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119 .DIR(P_2V8) |
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120 ); |
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121 |
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122 header_5pin J3 (.pin_1(GND), |
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123 .pin_2(Calypso_UART_CTS), |
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124 .pin_3(Calypso_UART_TxD), |
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125 .pin_4(Calypso_UART_RxD), |
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126 .pin_5(Calypso_UART_RTS) |
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127 ); |
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128 |
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129 endmodule |