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annotate mmtb1/schem+bom/vsrc/interface.v @ 44:635eab0b714e

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duart28: U5 & U6 slot change by PCB layout engineer
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 28 Jul 2020 17:01:37 +0000
parents 0f9bdd60ce50
children
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1 /*
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2 * This module encapsulates the FPC interface connector.
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3 */
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4
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5 module interface (GND, VBAT, PWON, nTESTRESET, Vio,
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6 TX_IRDA, RX_IRDA,
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7 TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM,
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8 GPIO2_DCD, GPIO3_DTR,
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9 VSIM, SIM_IO, SIM_CLK, SIM_RST,
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10 EARP, EARN, MICP, MICN);
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11
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12 input GND, VBAT, PWON, nTESTRESET;
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13 output Vio;
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14
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15 input GPIO3_DTR, RX_MODEM, CTS_MODEM, RX_IRDA;
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16 output GPIO2_DCD, TX_MODEM, RTS_MODEM, TX_IRDA;
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17
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18 output VSIM, SIM_CLK, SIM_RST;
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19 inout SIM_IO;
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20
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21 output EARP, EARN;
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22 input MICP, MICN;
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23
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24 /* instantiate the connector! */
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25
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26 conn_40pin_plus2 fpc_conn (.pin_1(VBAT),
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27 .pin_2(VBAT),
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28 .pin_3(VBAT),
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29 .pin_4(VBAT),
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30 .pin_5(VBAT),
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31 .pin_6(GND),
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32 .pin_7(GND),
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33 .pin_8(GND),
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34 .pin_9(GND),
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35 .pin_10(GND),
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36 .pin_11(TX_IRDA),
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37 .pin_12(RX_IRDA),
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38 .pin_13(Vio),
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39 .pin_14(), /* no connect to ADC */
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40 .pin_15(PWON),
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41 .pin_16(), /* no connect to GPIO1 */
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42 .pin_17(), /* no connect to GPIO0 */
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43 .pin_18(TX_MODEM),
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44 .pin_19(RX_MODEM),
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45 .pin_20(RTS_MODEM),
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46 .pin_21(CTS_MODEM),
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47 .pin_22(GPIO3_DTR),
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48 .pin_23(GPIO2_DCD),
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49 .pin_24(Vio), /* SIM_CD to Vio per TI/OM/FC */
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50 .pin_25(SIM_RST),
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51 .pin_26(SIM_IO),
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52 .pin_27(SIM_CLK),
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53 .pin_28(VSIM),
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54 .pin_29(GND), /* for SIM */
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55 .pin_30(), /* no connect to Vbackup */
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56 .pin_31(nTESTRESET),
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57 /*
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58 * Pins 32-40 differ between GTM900 and FCM40.
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59 * We connect EARP&EARN and MICP&MICN per GTM900
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60 * and leave the rest unconnected on MMTB1.
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61 */
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62 .pin_32(),
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63 .pin_33(),
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64 .pin_34(),
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65 .pin_35(EARP),
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66 .pin_36(EARN),
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67 .pin_37(MICP),
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68 .pin_38(MICN),
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69 .pin_39(),
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70 .pin_40(),
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71 /* ground the two mounting pads */
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72 .pin_41(GND),
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73 .pin_42(GND)
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74 );
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75
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76 endmodule