FreeCalypso > hg > fc-small-hw

annotate mmtb1/schem+bom/vsrc/uart_bringout.v @ 80:6bd0e0627938

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sim-fpc-pasv: starting project with MCL
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 25 Oct 2022 03:17:34 +0000
parents 0f9bdd60ce50
children
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1 /*
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2 * This Verilog module encapsulates the header connector on which
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3 * the two Calypso UARTs will be brought out.
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4 */
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5
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6 module uart_bringout (GND, TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM,
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7 GPIO_DCD, GPIO_DTR, TX_IRDA, RX_IRDA);
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8
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9 input GND;
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11 input TX_MODEM, RTS_MODEM, TX_IRDA, GPIO_DCD;
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12 output RX_MODEM, CTS_MODEM, RX_IRDA, GPIO_DTR;
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14 header_10pin uart_header (.pin_1(GND),
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15 .pin_2(GND),
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16 .pin_3(TX_IRDA),
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17 .pin_4(TX_MODEM),
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18 .pin_5(RX_IRDA),
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19 .pin_6(RX_MODEM),
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20 .pin_7(GPIO_DCD),
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21 .pin_8(RTS_MODEM),
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22 .pin_9(GPIO_DTR),
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23 .pin_10(CTS_MODEM)
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24 );
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26 endmodule