FreeCalypso > hg > fc-small-hw
annotate duart28/src/vsrc/regulator_ic.v @ 67:a1d59c66a410
lunalcd2/pcb: add Makefile
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 25 Jun 2021 23:08:00 +0000 |
parents | 22aba3a61a4b |
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rev | line source |
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22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 module regulator_ic (IN, OUT, GND, EN); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 input IN, GND, EN; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 output OUT; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 pkg_5pin pkg ( .pin_1(IN), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 .pin_2(GND), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 .pin_3(EN), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 .pin_4(), /* no connect */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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10 .pin_5(OUT) |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 ); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 endmodule |