FreeCalypso > hg > fc-small-hw
annotate duart28/src/vsrc/FT2232D_block.v @ 75:bb736a53463d
lunalcd3.pcb: extend ground plane for top bracket addition
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Thu, 18 Nov 2021 06:45:36 +0000 |
parents | 5d6823a08a5f |
children |
rev | line source |
---|---|
23
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 /* |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 * This module encapsulates the FT2232D chip and its immediate accessories: |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 * the oscillator crystal, the EEPROM, the AVCC filter and the cap on 3V3OUT. |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 module FT2232D_block (GND, VCC, VCCIOA, VCCIOB, |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 USBDP, USBDM, RESET, RSTOUT, PWREN, |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 input GND, VCC, VCCIOA, VCCIOB; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 inout USBDP, USBDM; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 input RESET; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 output RSTOUT, PWREN; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 inout [7:0] ADBUS, BDBUS; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 inout [3:0] ACBUS, BCBUS; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
19 input SI_WUA, SI_WUB; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
20 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
21 /* FT2232D pins handled within this block */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
22 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
23 wire EECS, EESK, EEDATA; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
24 wire XTIN, XTOUT; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
25 wire AVCC, FTDI_3V3; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
26 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
27 /* instantiate the FT2232D */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
28 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
29 FT2232D_chip FT2232D (.GND(GND), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
30 .AGND(GND), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
31 .VCC(VCC), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
32 .AVCC(AVCC), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
33 .VCCIOA(VCCIOA), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
34 .VCCIOB(VCCIOB), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
35 .OUT_3V3(FTDI_3V3), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
36 .USBDP(USBDP), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
37 .USBDM(USBDM), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
38 .EECS(EECS), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
39 .EESK(EESK), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
40 .EEDATA(EEDATA), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
41 .RESET(RESET), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
42 .RSTOUT(RSTOUT), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
43 .TEST(GND), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
44 .PWREN(PWREN), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
45 .XTIN(XTIN), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
46 .XTOUT(XTOUT), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
47 .ADBUS(ADBUS), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
48 .ACBUS(ACBUS), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
49 .SI_WUA(SI_WUA), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
50 .BDBUS(BDBUS), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
51 .BCBUS(BCBUS), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
52 .SI_WUB(SI_WUB) |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
53 ); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
54 |
31
5d6823a08a5f
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Mychaela Falconia <falcon@freecalypso.org>
parents:
23
diff
changeset
|
55 /* VCCIO bypass caps */ |
5d6823a08a5f
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Mychaela Falconia <falcon@freecalypso.org>
parents:
23
diff
changeset
|
56 |
5d6823a08a5f
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Mychaela Falconia <falcon@freecalypso.org>
parents:
23
diff
changeset
|
57 capacitor VCCIOA_bypass_cap (VCCIOA, GND); |
5d6823a08a5f
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Mychaela Falconia <falcon@freecalypso.org>
parents:
23
diff
changeset
|
58 capacitor VCCIOB_bypass_cap (VCCIOB, GND); |
5d6823a08a5f
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Mychaela Falconia <falcon@freecalypso.org>
parents:
23
diff
changeset
|
59 |
23
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
60 /* AVCC filter */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
61 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
62 resistor AVCC_filter_R (VCC, AVCC); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
63 capacitor AVCC_cap (AVCC, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
64 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
65 /* 3V3OUT */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
66 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
67 capacitor FTDI_3V3_cap (FTDI_3V3, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
68 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
69 /* crystal oscillator */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
70 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
71 xtal_2pin_pkg xtal (XTIN, XTOUT); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
72 capacitor XTIN_cap (XTIN, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
73 capacitor XTOUT_cap (XTOUT, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
74 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
75 /* serial EEPROM */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
76 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
77 wire EEPROM_DOUT; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
78 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
79 eeprom_93Cx6_16bit eeprom (.GND(GND), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
80 .VCC(VCC), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
81 .CS(EECS), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
82 .SK(EESK), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
83 .DIN(EEDATA), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
84 .DOUT(EEPROM_DOUT) |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
85 ); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
86 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
87 resistor DOUT_series_R (EEPROM_DOUT, EEDATA); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
88 resistor DOUT_pullup_R (EEPROM_DOUT, VCC); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
89 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
90 endmodule |