FreeCalypso > hg > fc-small-hw

annotate duart28/src/vsrc/board.v @ 75:bb736a53463d

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd3.pcb: extend ground plane for top bracket addition
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Nov 2021 06:45:36 +0000
parents bd7eec55ebc0
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 module board ();
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 wire GND, P_5V, P_3V3, P_2V8;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 wire [7:0] ADBUS, BDBUS;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 wire [3:0] ACBUS, BCBUS;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 USB_block usb ( .GND(GND),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 .P_5V(P_5V),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 .VCCIOA(P_3V3),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 .VCCIOB(P_3V3),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 .ADBUS(ADBUS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 .ACBUS(ACBUS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 .SI_WUA(P_3V3),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 .BDBUS(BDBUS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 .BCBUS(BCBUS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 .SI_WUB(P_3V3),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 .PWREN() /* no connect */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 );
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3));
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8));
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 application_block app ( .GND(GND),
28
bd7eec55ebc0 duart28: new design ideas
Mychaela Falconia <falcon@freecalypso.org>
parents: 24
diff changeset
25 .P_3V3(P_3V3),
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 .P_2V8(P_2V8),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27 .ADBUS(ADBUS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 .BDBUS(BDBUS)
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 );
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30
24
9e71844f4db0 duart28/src/vsrc/board.v: aux_5V added
Mychaela Falconia <falcon@freecalypso.org>
parents: 23
diff changeset
31 /* auxiliary 5V output */
9e71844f4db0 duart28/src/vsrc/board.v: aux_5V added
Mychaela Falconia <falcon@freecalypso.org>
parents: 23
diff changeset
32
9e71844f4db0 duart28/src/vsrc/board.v: aux_5V added
Mychaela Falconia <falcon@freecalypso.org>
parents: 23
diff changeset
33 header_2pin aux_5V (.pin_1(P_5V),
9e71844f4db0 duart28/src/vsrc/board.v: aux_5V added
Mychaela Falconia <falcon@freecalypso.org>
parents: 23
diff changeset
34 .pin_2(GND)
9e71844f4db0 duart28/src/vsrc/board.v: aux_5V added
Mychaela Falconia <falcon@freecalypso.org>
parents: 23
diff changeset
35 );
9e71844f4db0 duart28/src/vsrc/board.v: aux_5V added
Mychaela Falconia <falcon@freecalypso.org>
parents: 23
diff changeset
36
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37 endmodule