FreeCalypso > hg > fc-small-hw
annotate duart28/src/vsrc/regulator_with_caps.v @ 28:bd7eec55ebc0
duart28: new design ideas
* added input buffers (LVC with Ioff feature) to prevent high current flow
from powered-up target into powered-down FT2232D inputs;
* added series resistors on outputs to limit current flow from powered-up
adapter into powered-down Calypso target;
* buffer IC changed from 74LVC125A to 74LVC541A.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sun, 28 Jun 2020 22:06:24 +0000 |
parents | 22aba3a61a4b |
children |
rev | line source |
---|---|
23
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 module regulator_with_caps (GND, IN, OUT); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 input GND, IN; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 output OUT; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 regulator_ic reg (.IN(IN), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 .OUT(OUT), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 .GND(GND), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 .EN(IN) |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 ); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 capacitor input_cap (IN, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 capacitor output_cap (OUT, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 endmodule |