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annotate duart28/design-spec @ 72:c2a3670c7aca

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lunalcd3.pcb: manually add bottom strap to LCD footprint
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Nov 2021 06:11:27 +0000
parents 45bbb72a8916
children
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34
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Mychaela Falconia <falcon@freecalypso.org>
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1 FreeCalypso DUART28 Adapter
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Mychaela Falconia <falcon@freecalypso.org>
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2 Board design specification
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3
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Mychaela Falconia <falcon@freecalypso.org>
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4 1. What it is and why it is desired
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5
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Mychaela Falconia <falcon@freecalypso.org>
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6 Under our FreeCalypso umbrella we have a family of hardware products based on
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Mychaela Falconia <falcon@freecalypso.org>
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7 the Calypso chipset from Texas Instruments. The Calypso chip has two UARTs,
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Mychaela Falconia <falcon@freecalypso.org>
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8 one with TxD & RxD data leads plus RTS & CTS flow control, and the other with
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Mychaela Falconia <falcon@freecalypso.org>
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9 TxD & RxD data leads only. There is also a convention whereby some Calypso
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Mychaela Falconia <falcon@freecalypso.org>
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10 GPIOs are defined to be additional modem control signals and associated with
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Mychaela Falconia <falcon@freecalypso.org>
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11 the Modem UART (the one that has RTS & CTS flow control in addition to
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Mychaela Falconia <falcon@freecalypso.org>
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12 TxD & RxD), thus the result is one UART with a near-complete set of modem
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Mychaela Falconia <falcon@freecalypso.org>
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13 control signals and one UART with data leads only.
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14
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Mychaela Falconia <falcon@freecalypso.org>
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15 The convention established in FreeCalypso is that all of our Calypso development
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Mychaela Falconia <falcon@freecalypso.org>
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16 boards bring out both Calypso UARTs in their native form, which is 2.8V native
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Mychaela Falconia <falcon@freecalypso.org>
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17 logic levels, tolerant of 3.3V but not any higher voltages. In order to connect
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Mychaela Falconia <falcon@freecalypso.org>
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18 these UARTs to a PC or laptop serving as the development host, a separate USB
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Mychaela Falconia <falcon@freecalypso.org>
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19 to low-voltage UART adapter board is used, preferably one that puts both UARTs
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Mychaela Falconia <falcon@freecalypso.org>
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20 (two ttyUSBx devices) behind a single USB device. Our USB to dual UART
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Mychaela Falconia <falcon@freecalypso.org>
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21 converter chip of choice is FT2232D; this chip has been chosen over various
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Mychaela Falconia <falcon@freecalypso.org>
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22 competitors because it provides two UART channels (ttyUSBx devices) in one USB
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23 device, because it supports non-standard serial baud rates on both channels,
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24 allowing us to use GSM-specific high baud rates of 203125, 406250 and 812500
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Mychaela Falconia <falcon@freecalypso.org>
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25 bps, and because it supports the full set of modem control signals like one
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Mychaela Falconia <falcon@freecalypso.org>
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26 would find on an old-fashioned RS-232 port.
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27
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Mychaela Falconia <falcon@freecalypso.org>
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28 Since we got our first FCDEV3B boards built in 2017 and up until the present,
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Mychaela Falconia <falcon@freecalypso.org>
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29 we've been using FT2232D breakout boards made by PLDkit as our USB to dual UART
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Mychaela Falconia <falcon@freecalypso.org>
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30 adapter:
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31
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32 http://pldkit.com/other/ft2232d-module
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33
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34 These generic FT2232D adapters work quite well for our current purposes, but
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Mychaela Falconia <falcon@freecalypso.org>
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35 now we have several reasons for desiring our own custom-built adapter to
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Mychaela Falconia <falcon@freecalypso.org>
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36 replace them, detailed below.
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37
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Mychaela Falconia <falcon@freecalypso.org>
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38 1.1. Desire for custom interface pinout
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39
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Mychaela Falconia <falcon@freecalypso.org>
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40 In FreeCalypso we have the following convention: all FC hardware products that
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Mychaela Falconia <falcon@freecalypso.org>
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41 bring out both Calypso UARTs do so by way of a single 10-pin (2x5) 2.54 mm
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Mychaela Falconia <falcon@freecalypso.org>
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42 header in a fixed pinout given below. This convention was started with
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Mychaela Falconia <falcon@freecalypso.org>
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43 FCDEV3B, our first FC hw product, and is now being continued with MMTB1 and
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Mychaela Falconia <falcon@freecalypso.org>
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44 Caramel2 boards. Our standardized DUART header pinout is as follows:
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45
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Mychaela Falconia <falcon@freecalypso.org>
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46 Header pin Calypso signal
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Mychaela Falconia <falcon@freecalypso.org>
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47 1 GND
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48 2 GND
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49 3 TX_IRDA
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50 4 TX_MODEM
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51 5 RX_IRDA
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52 6 RX_MODEM
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53 7 GPIO2_DCD
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Mychaela Falconia <falcon@freecalypso.org>
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54 8 RTS_MODEM
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Mychaela Falconia <falcon@freecalypso.org>
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55 9 GPIO3_DTR
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Mychaela Falconia <falcon@freecalypso.org>
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56 10 CTS_MODEM
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57
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Mychaela Falconia <falcon@freecalypso.org>
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58 Pins 7 and 9 were originally left unused (they are unconnected on FCDEV3B), but
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Mychaela Falconia <falcon@freecalypso.org>
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59 they have been assigned as DCD and DTR (from the host's perspective) starting
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Mychaela Falconia <falcon@freecalypso.org>
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60 with MMTB1. Note that while DCD and DTR in the table above are named from the
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Mychaela Falconia <falcon@freecalypso.org>
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61 host's perspective, all Calypso signals ending with _MODEM or _IRDA are from
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Mychaela Falconia <falcon@freecalypso.org>
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62 the chip's perspective, i.e., the opposite.
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63
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Mychaela Falconia <falcon@freecalypso.org>
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64 When we use FT2232D breakout boards from PLDkit as our USB to DUART adapter, we
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Mychaela Falconia <falcon@freecalypso.org>
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65 use a custom hand-made ribbon cable with crimp terminations: a 10-wire ribbon
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Mychaela Falconia <falcon@freecalypso.org>
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66 is used, the full ribbon runs intact in the main body of the cable, but toward
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Mychaela Falconia <falcon@freecalypso.org>
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67 the FT2232D adapter board the ribbon is split in two, with 7 wires going to the
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Mychaela Falconia <falcon@freecalypso.org>
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68 A side of PLDkit's breakout board and with 3 wires going to the B side. Each
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Mychaela Falconia <falcon@freecalypso.org>
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69 of the two subribbons (both the 7-wire one and the 3-wire one) gets terminated
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70 onto a 15-position female connector, with the two resulting 15-pin connectors
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71 mating with the two 15-pin single-row headers located on the two sides of
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Mychaela Falconia <falcon@freecalypso.org>
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72 PLDkit's breakout board.
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73
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Mychaela Falconia <falcon@freecalypso.org>
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74 This current solution is much better than manually connecting each wire
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Mychaela Falconia <falcon@freecalypso.org>
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75 individually: with connectors being solid pieces rather than individual wires,
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Mychaela Falconia <falcon@freecalypso.org>
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76 a setup can be very easily taken down and then put back together, which is
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Mychaela Falconia <falcon@freecalypso.org>
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77 absolutely essential for our mode of usage. But the downside of this approach
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78 is that once our two 15-position female connectors mate with PLDkit's headers,
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Mychaela Falconia <falcon@freecalypso.org>
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79 there is no way to make a separate connection to other signals which are not
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80 covered by our basic 10-wire set. This limitation is becoming problematic for
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Mychaela Falconia <falcon@freecalypso.org>
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81 two reasons:
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82
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83 1) Our upcoming Caramel2 board will have the same 10-pin DUART header as FCDEV3B
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Mychaela Falconia <falcon@freecalypso.org>
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84 and MMTB1 (with DCD & DTR present like on MMTB1), but it will also have an
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Mychaela Falconia <falcon@freecalypso.org>
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85 additional RI modem control output on another Calypso GPIO accessible on the
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Mychaela Falconia <falcon@freecalypso.org>
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86 general expansion interface header. There is no room to squeeze this extra RI
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Mychaela Falconia <falcon@freecalypso.org>
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87 signal into our standardized 10-pin DUART interface, but this extra signal is
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Mychaela Falconia <falcon@freecalypso.org>
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88 rarely needed. The compromise solution currently being pursued is that the
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Mychaela Falconia <falcon@freecalypso.org>
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89 main 10-wire ribbon will connect all UART signals (both UARTs) with the
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Mychaela Falconia <falcon@freecalypso.org>
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90 exception of RI, and those who need RI should be able to connect it with a
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Mychaela Falconia <falcon@freecalypso.org>
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91 separate individual wire, connecting to the GPIO1 pin on the general expansion
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Mychaela Falconia <falcon@freecalypso.org>
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92 interface header on the Caramel2 side. But if we use PLDkit breakout boards
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Mychaela Falconia <falcon@freecalypso.org>
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93 with our current ribbon cables with crimp terminations, there will be no way to
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Mychaela Falconia <falcon@freecalypso.org>
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94 connect this extra RI wire to the FT2232D adapter board when the big 15-pin
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95 connector blocks the entire header.
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96
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97 2) PLDkit's FT2232D breakout boards bring out USB 5V on one of their pins, and
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Mychaela Falconia <falcon@freecalypso.org>
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98 this auxiliary 5V output is useful in some applications. We have one upcoming
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Mychaela Falconia <falcon@freecalypso.org>
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99 application where this auxiliary 5V will be used to exercise the Calypso+Iota
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Mychaela Falconia <falcon@freecalypso.org>
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100 chipset's VCHG boot mode, also on the upcoming Caramel2 board - but we get into
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Mychaela Falconia <falcon@freecalypso.org>
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101 the same problem of the PLDkit board header pin becoming inaccessible when our
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Mychaela Falconia <falcon@freecalypso.org>
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102 crimp-terminated ribbon cables are used.
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103
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104 If we replace the generic PLDkit breakout with our own custom FreeCalypso USB
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Mychaela Falconia <falcon@freecalypso.org>
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105 to dual UART adapter board, we can easily solve these problems by implementing
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106 our own custom header pinouts. The new DUART28 adapter board covered by the
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Mychaela Falconia <falcon@freecalypso.org>
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107 present design spec will bring out 3 headers as follows:
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108
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109 * One 10-pin header carrying TxD, RxD, RTS, CTS, DTR and DCD for UART 0 and
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110 just TxD & RxD for UART 1, in a pinout exactly matching our standardized
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Mychaela Falconia <falcon@freecalypso.org>
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111 FreeCalypso DUART interface;
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112
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113 * One 3-pin header carrying UART 0 auxiliary modem control inputs DSR and RI,
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Mychaela Falconia <falcon@freecalypso.org>
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114 plus a ground pin;
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115
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116 * One 2-pin header bringing out USB 5V and GND, for auxiliary uses.
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117
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118 1.2. 3.3V vs. 2.8V logic levels
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119
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120 Calypso I/O pins have native 2.8V logic levels, but they are specified as being
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Mychaela Falconia <falcon@freecalypso.org>
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121 tolerant of 3.3V. They do have internal clamping diodes to the Calypso chip's
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Mychaela Falconia <falcon@freecalypso.org>
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122 2.8V V-IO rail, but their forward drop voltage is right around 0.5 V, thus if
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Mychaela Falconia <falcon@freecalypso.org>
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123 external inputs are at 0.5 V above V-IO (practically meaning 3.3V inputs), no
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Mychaela Falconia <falcon@freecalypso.org>
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124 significant current flows through these clamping diodes.
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125
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126 When we use a raw FT2232D breakout board as our USB to FreeCalypso DUART
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127 adapter, we are connecting the FT2232D chip's 3.3V outputs directly to Calypso
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Mychaela Falconia <falcon@freecalypso.org>
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128 inputs; this arrangement has been working well for us since 2017, but a more
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Mychaela Falconia <falcon@freecalypso.org>
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129 proper 2.8V DUART adapter is desirable for a few reasons:
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130
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131 * When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for
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132 Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO
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133 regulator (the one that produces the 2.8V V-IO rail) switches into sleep mode,
34
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134 which has much looser regulation than in the regular Active mode. In this
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135 condition external 3.3V can feed into the V-IO rail through pull-up resistors
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136 and pull the rail itself a little higher than where the chipset's own regulators
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137 would have it, which is certainly not desirable. If UART inputs to the Calypso
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138 board are driven with 2.8V logic levels rather than 3.3V, this problem is not
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139 expected to occur.
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140
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141 * If we are going to build a custom FreeCalypso DUART adapter for other reasons,
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142 it is only proper to make it 2.8V native rather than 3.3V - after all, our
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143 adapter is highly specific to Calypso applications, not generic, and Calypso
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144 has native 2.8V I/O.
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145
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146 * We have a competitor: Sysmocom folks use CP2105 adapters (mv-uart adapter
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147 board and other integrated designs) instead of our FT2232D, and their
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148 CP2105-based designs operate at native 2.8V logic levels, no 3.3V. For
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149 political reasons it is important to be no worse than the competition, giving
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150 us one more reason to go for native 2.8V.
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151
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152 Because FT2232D I/O (unlike CP2105, FT232R and many other chips that aren't
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153 suitable for other reasons) cannot go below 3.3V, making an FT2232D-based
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154 adapter put out 2.8V logic levels requires inserting an extra level shifter
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155 after FT2232D outputs - we shall use an LVC buffer for this purpose.
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156
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157 1.3. Partial power-down considerations
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158
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159 The following two corner cases need to be considered, as each can be a trouble
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160 spot:
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161
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162 1) When the USB to DUART adapter is connected to a host computer and thus has
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163 USB power present, but the connected Calypso device is in the switched-off
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164 state in the Iota VRPC sense (a condition that occurs all the time in normal
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165 operation, e.g., whenever you are running fc-loadtool and waiting to press the
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166 PWON button on the board), current can flow from USB DUART adapter outputs into
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167 powered-down Calypso chip inputs. This current flow cannot be eliminated
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168 without putting LVC or similar buffers on the Calypso board side, but we need
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parents:
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169 to be mindful of this current and we need to limit it.
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170
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171 2) When a Calypso device is connected to the USB DUART adapter, the Calypso
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172 device is up and running (VRPC Active state), but there is no USB host
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173 connected, current can flow from Calypso outputs into a powered-down FT2232D
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174 (or other front-end chips) in the USB DUART adapter. With our current raw
37
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175 FT2232D-to-Calypso arrangement we have about 5.8 mA of current flowing per pin
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176 under the described condition, which is way too much.
34
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177
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178 If we replace the generic FT2232D breakout with our own custom adapter board
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179 design, we can solve the second partial power-down problem (the case of Calypso
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180 on, but no USB host) by inserting LVC buffers in front of FT2232D inputs -
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181 these LVC buffers are fully specified for partial power-down applications and
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182 have very small Ioff leakage current.
36
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183
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184 2. Circuit design
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185
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186 2.1. FT2232D core section
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187
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188 Our FT2232D core section (basically everything from the USB connector to the
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189 FT2232D chip's ADBUS and BDBUS interfaces) is based on PLDkit's generic FT2232D
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190 module:
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191
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192 ftp://ftp.freecalypso.org/pub/USB/FTDI/FT2232D_module_B_schematics.pdf
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193
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194 This core section is essentially boilerplate in which we have zero desire for
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195 innovation, hence we would like to copy it from a known-working design. In
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196 this project the section in question has been recaptured in our ueda language
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197 based on the above schematic drawing.
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198
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199 2.2. UART outputs from the adapter
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200
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201 We have a total of 4 outputs: TxD, RTS, DTR and TxD2. Because we wish to put
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202 out 2.8V logic levels rather than 3.3V, each output needs to pass through an
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203 LVC buffer; we use a 74LVC541A as our buffer IC.
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204
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205 There is also a series resistor inserted into each output after the LVC buffer;
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206 the initial value to be populated on the first board build is 2.2 kOhm, to be
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207 further tuned empirically. The purpose of these series resistors is to limit
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208 the current that will flow from our DUART28 adapter into the Calypso target
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209 when the Calypso is powered down - see section 1.3. In our current setup with
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210 direct FT2232D to Calypso connection (no series resistors) this current has
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211 been measured to be somewhere around 1.77 mA, and it appears to be limited by
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parents: 35
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212 the current sourcing ability of FT2232D drivers (1 mA per datasheet). However,
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parents: 35
diff changeset
213 our new LVC buffers have much stronger drivers, specified to both source and
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214 sink up to 24 mA, thus series resistors become mandatory for proper operation
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215 in this partial power-down scenario.
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216
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217 The value of these series resistors is a delicate tuning job: they need to be
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218 large enough to limit current flow in the partial power-down scenario, but they
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parents: 35
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219 cannot be too large, or they will adversely affect serial communication. Each
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220 of these series resistors will form an RC circuit together with various
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parents: 35
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221 parasitic capacitances on the Calypso target side; larger R translates to a
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parents: 35
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222 larger RC time constant, resulting in slower signal rise and fall times,
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223 adversely affecting serial communication at higher baud rates.
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224
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225 We have an existing Calypso development board produced by another company that
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226 features old-fashioned RS-232 interfaces (classic DE9F connectors) and uses an
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parents: 35
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227 on-board RS-232 to LVTTL/LVCMOS converter; this board features 1 kOhm series
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parents: 35
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228 resistors in the same place as in our proposed design, and it works fine at
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229 812500 baud. If we populate the same 1 kOhm resistors, the undesirable current
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parents: 35
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230 in the partial power-down scenario will be 2.8 mA per pin, which is greater
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parents: 35
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231 than our current 1.77 mA; with our current plan of populating 2.2 kOhm resistors
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parents: 35
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232 the current will be 1.27 mA, and we are hoping that 812500 baud communication
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parents: 35
diff changeset
233 will still work OK.
38
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234
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235 2.3. UART inputs to the adapter
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236
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237 We have a total of 6 inputs: RxD, CTS, DSR, DCD, RI and RxD2. These inputs
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parents: 37
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238 need to pass through LVC buffers just like the outputs, but for a different
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parents: 37
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239 reason. With inputs there is no need for voltage level translation, but the
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parents: 37
diff changeset
240 need for LVC buffers arises because of partial power-down considerations - the
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parents: 37
diff changeset
241 scenario when the Calypso board is fully up and running and is connected to the
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parents: 37
diff changeset
242 DUART adapter, but there is no USB host connected - see section 1.3. If
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parents: 37
diff changeset
243 Calypso UART outputs are connected directly to FT2232D inputs without any
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parents: 37
diff changeset
244 intermediate buffers, this condition is handled very poorly, with about 5.8 mA
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parents: 37
diff changeset
245 of current flowing per pin, which is certainly not acceptable for a proper
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parents: 37
diff changeset
246 design.
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247
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248 Insertion of an LVC buffer into each input signal path neatly solves this
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diff changeset
249 problem: these buffers are specifically designed for partial power-down
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parents: 37
diff changeset
250 applications and have very small Ioff leakage current - listed as 0.1 uA
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parents: 37
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251 typical or 10 uA maximum in the 74LVC541A datasheet.
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252
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253 One additional complication is that we also have to add explicit pull-up
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diff changeset
254 resistors (to our local 2.8V rail) on each of our 6 inputs in front of the
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255 buffer IC. Many of our UART inputs may be legitimately left unconnected, and
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parents: 37
diff changeset
256 these unconnected inputs should be sensed by our FT2232D USB UART as high. If
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parents: 37
diff changeset
257 we were connecting to FT2232D inputs directly, the FT2232D chip's internal
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258 pull-ups would take care of this condition, but when we have a 74LVC541A buffer
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259 in front of these FT2232D inputs, this buffer IC's own inputs must not be left
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260 floating.
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261
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262 2.4. LVC buffer details
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263
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264 We shall use two LVC buffer ICs of the same type (74LVC541A), one for the 4
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265 outputs, the other for the 6 inputs. Each 74LVC541A is an octal buffer, thus
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266 some slots in each IC remain unused; all unused slots will have their A inputs
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267 tied to GND. Both nOE1 and nOE2 on each buffer IC are also tied to GND,
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268 resulting in all buffers being always enabled.
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269
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270 The 74LVC541A buffer for outputs will have its Vcc supply pin fed with 2.8V, as
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271 required in order to produce 2.8V logic levels on outputs from the adapter.
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272 However, the other 74LVC541A buffer for inputs will have its Vcc supply pin fed
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273 with 3.3V, same as FT2232D VCCIOA and VCCIOB.
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274
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275 When the inputs coming from the connected Calypso target have 2.8V logic levels
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276 and ultimately need to go to FT2232D receivers operating at 3.3V, a sort of
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277 translation will have to happen somewhere, with a CMOS input structure operating
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278 with a 3.3V supply being fed 2.8V inputs. We can make this translation happen
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279 in the FT2232D if we use an intermediate LVC buffer powered at 2.8V or no
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280 intermediate buffer at all, or we can make this translation happen in the LVC
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281 buffer if the latter is powered with the same 3.3V as the FT2232D I/O pins.
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282 The second approach has been chosen because the behaviour of 74LVC541A under
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283 these conditions is much better understood than the behaviour of FT2232D I/O
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284 cells under the same, thanks to much better documentation being available for
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285 74LVC541A than for that part of FT2232D.
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286
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287 Please note, however, that the pull-up resistors on inputs before input-serving
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288 74LVC541A buffer will be wired to our local 2.8V rail, not to 3.3V, even though
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289 the buffer IC will be powered with 3.3V. This way all interface signals exist
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290 strictly in the 2.8V domain and never get exposed to 3.3V in any form.
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291
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292 2.5. LDO regulators
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293
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294 Two LDO regulators will be implemented on our adapter board, both powered from
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295 USB 5V: one producing 3.3V, the other producing 2.8V. Our 3.3V LDO will power
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296 FT2232D VCCIOA & VCCIOB and the input-serving 74LVC541A buffer, whereas the
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297 other 2.8V LDO will power our output-serving 74LVC541A buffer and our input
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298 pull-up resistors. Both LDOs will be of TLV702 family from TI, based on our
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299 recent good experiences with this LDO family in other projects.
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300
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301 The FT2232D chip's built-in 3.3V LDO won't be used: its 5 mA current limit
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302 seems to be too small, and our current FT2232D adapter boards made by PLDkit
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303 don't use it either, using an external beefier LDO instead.
41
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304
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305 3. PCB layout specification
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306
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307 3.1. Overall dimensions
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308
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309 The generic FT2232D breakout board from PLDkit which the present DUART28 seeks
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310 to replace measures 39.37x46.99 mm or 1550x1850 mil. If the present DUART28
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311 circuit can be squeezed into the same size, great - but such squeeze is NOT
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312 required. If our DUART28 requires a larger PCB because of our greater circuit
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313 complexity and having more components, using a larger PCB would be perfectly
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314 fine - however much space is needed to get the job done. There is no specific
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315 form factor requirement, i.e., this project is a free-form design.
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316
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317 3.2. Layer count
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318
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319 PLDkit's FT2232D adapter board appears to have a 2-layer PCB, and our competitor
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320 mv-uart by Sysmocom (CP2105-based) is known to have a 2-layer PCB thanks to
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321 published design files. However, we shall go by the same business logic as with
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322 board dimensions: if the needed layout can be done in just 2 layers, great, but
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323 if the PCB layout engineer feels that going to 4 layers would be better or would
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324 make the layout job easier, it would be perfectly OK to have 4 layers.
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325
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326 3.3. Mounting holes
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327
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328 The PCB should have 4 mounting holes in the corners, accommodating M3 screws.
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329 It is OK to increase overall board dimensions slightly to make room for these
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330 mounting holes.
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331
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332 3.4. Placement of connectors
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333
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334 USB mini-B connector J1 must be placed along one of the board edges; it does not
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335 matter along which edge, or exactly where.
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336
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337 Shrouded 2x5 header J2 can be placed anywhere, as long as the placement makes
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338 sense for cable attachment purposes. The cable plugged into this connector will
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339 be a 10-wire ribbon terminated with an IDC connector, thus the body of the flat
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340 cable will lie parallel to the board surface. Orientation: the body of the
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341 cable will face toward the even-numbered row of pins, i.e., away from the
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342 polarizing tab identified with a silk screen mark in the currently drawn
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343 footprint.
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344
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345 Little headers J3 and J4 can be placed anywhere; they are not shrouded and the
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346 only things that can be connected to them are either individual jumper wires or
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347 crimped assemblies with wires rising up, perpendicular to the board.
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348
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349 3.5. Connector silk screen labels
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350
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351 All three user connection headers J2, J3 and J4 shall have silk screen labels
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352 identifying every pin. J2 pins shall be labeled as follows, numbers in the
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353 middle indicate physical pins and shall NOT be placed on the silk screen
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354 themselves:
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355
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356 GND 1 2 GND
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357 RxD2 3 4 RxD
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358 TxD2 5 6 TxD
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359 DCD 7 8 CTS
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360 DTR 9 10 RTS
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361
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362 J3 pins shall be labeled as follows, numbers on the left indicate physical pins
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363 and shall NOT be placed on the silk screen themselves:
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364
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365 1 GND
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366 2 DSR
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367 3 RI
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368
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369 J4 pins shall be labeled as follows, same deal with pin numbers:
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370
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371 1 +5V
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372 2 GND
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373
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374 3.6. 74LVC541A slot assignment
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375
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376 74LVC541A is an octal buffer IC that can be seen as a bundle of 8 single buffers
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377 with common output enables; the latter are always enabled in our present
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378 circuit. The present design uses two of these octal buffer ICs (see section
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379 2.4): one with 4 signals and 4 unused slots (grounded A inputs, unconnected Y
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380 outputs) and one with 6 signals and 2 unused slots. The mapping of which signal
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381 should go to which An/Yn slot is arbitrary from the standpoint of circuit
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382 functionality, thus this mapping should be made at the time of PCB layout for
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383 physical layout optimization.
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384
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385 The mapping of signals to U5 and U6 slots is defined in U5.slotmap and
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386 U6.slotmap text files; to change these mappings, edit the two files to define
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387 the desired mapping, then recompile the netlist by running 'make', producing an
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388 updated pcb-netlist.txt generated file.
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389
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390 The preliminary slot mapping that exists in the present netlist was created as
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391 a placeholder to pass compilation, and is NOT expected to be anywhere close to
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392 optimal for layout! Therefore, the PCB layout engineer is expected to review
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393 this slot mapping and optimize it for layout.
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394
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395 3.7. Power bypass capacitors
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396
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397 By the very nature of power bypass capacitors, a netlist gives absolutely no
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398 indication as to where they need to be placed - yet their physical placement is
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399 essential to their circuit function. Because the design of this board is
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400 captured in ueda language instead of graphical schematics, it is possible that
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401 the PCB layout engineer may have some difficulty with reading our ueda design
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parents: 38
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402 source to understand the design intent as to where each bypass capacitor should
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parents: 38
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403 be placed. The following listing is intended to resolve this ambiguity:
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404
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405 * C4 and C7 need to be placed at the output of L1 on the P_5V net;
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parents: 38
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406 * C8 needs to be placed at the input of LDO regulator U3;
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parents: 38
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407 * C9 needs to be placed at the output of LDO regulator U3;
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parents: 38
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408 * C10 needs to be placed at the input of LDO regulator U4;
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parents: 38
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409 * C11 needs to be placed at the output of LDO regulator U4;
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parents: 38
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410 * C12 needs to be placed near pin 20 (Vcc) of U5;
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parents: 38
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411 * C13 needs to be placed near pin 20 (Vcc) of U6;
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parents: 38
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412 * C14 needs to be placed near pin 14 (VCCIOA) of U1;
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parents: 38
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413 * C15 needs to be placed near pin 31 (VCCIOB) of U1.