annotate duart28/design-spec @ 72:c2a3670c7aca

lunalcd3.pcb: manually add bottom strap to LCD footprint
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 18 Nov 2021 06:11:27 +0000
parents 45bbb72a8916
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
34
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 FreeCalypso DUART28 Adapter
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 Board design specification
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 1. What it is and why it is desired
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 Under our FreeCalypso umbrella we have a family of hardware products based on
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 the Calypso chipset from Texas Instruments. The Calypso chip has two UARTs,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 one with TxD & RxD data leads plus RTS & CTS flow control, and the other with
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 TxD & RxD data leads only. There is also a convention whereby some Calypso
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 GPIOs are defined to be additional modem control signals and associated with
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 the Modem UART (the one that has RTS & CTS flow control in addition to
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 TxD & RxD), thus the result is one UART with a near-complete set of modem
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 control signals and one UART with data leads only.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 The convention established in FreeCalypso is that all of our Calypso development
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 boards bring out both Calypso UARTs in their native form, which is 2.8V native
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 logic levels, tolerant of 3.3V but not any higher voltages. In order to connect
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 these UARTs to a PC or laptop serving as the development host, a separate USB
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 to low-voltage UART adapter board is used, preferably one that puts both UARTs
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 (two ttyUSBx devices) behind a single USB device. Our USB to dual UART
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 converter chip of choice is FT2232D; this chip has been chosen over various
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 competitors because it provides two UART channels (ttyUSBx devices) in one USB
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 device, because it supports non-standard serial baud rates on both channels,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 allowing us to use GSM-specific high baud rates of 203125, 406250 and 812500
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 bps, and because it supports the full set of modem control signals like one
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 would find on an old-fashioned RS-232 port.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 Since we got our first FCDEV3B boards built in 2017 and up until the present,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 we've been using FT2232D breakout boards made by PLDkit as our USB to dual UART
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 adapter:
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 http://pldkit.com/other/ft2232d-module
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34 These generic FT2232D adapters work quite well for our current purposes, but
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 now we have several reasons for desiring our own custom-built adapter to
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 replace them, detailed below.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 1.1. Desire for custom interface pinout
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 In FreeCalypso we have the following convention: all FC hardware products that
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 bring out both Calypso UARTs do so by way of a single 10-pin (2x5) 2.54 mm
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 header in a fixed pinout given below. This convention was started with
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43 FCDEV3B, our first FC hw product, and is now being continued with MMTB1 and
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 Caramel2 boards. Our standardized DUART header pinout is as follows:
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46 Header pin Calypso signal
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 1 GND
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 2 GND
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 3 TX_IRDA
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 4 TX_MODEM
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 5 RX_IRDA
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52 6 RX_MODEM
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53 7 GPIO2_DCD
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 8 RTS_MODEM
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 9 GPIO3_DTR
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 10 CTS_MODEM
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
57
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
58 Pins 7 and 9 were originally left unused (they are unconnected on FCDEV3B), but
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
59 they have been assigned as DCD and DTR (from the host's perspective) starting
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
60 with MMTB1. Note that while DCD and DTR in the table above are named from the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
61 host's perspective, all Calypso signals ending with _MODEM or _IRDA are from
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
62 the chip's perspective, i.e., the opposite.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
63
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
64 When we use FT2232D breakout boards from PLDkit as our USB to DUART adapter, we
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
65 use a custom hand-made ribbon cable with crimp terminations: a 10-wire ribbon
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
66 is used, the full ribbon runs intact in the main body of the cable, but toward
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
67 the FT2232D adapter board the ribbon is split in two, with 7 wires going to the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
68 A side of PLDkit's breakout board and with 3 wires going to the B side. Each
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
69 of the two subribbons (both the 7-wire one and the 3-wire one) gets terminated
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
70 onto a 15-position female connector, with the two resulting 15-pin connectors
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
71 mating with the two 15-pin single-row headers located on the two sides of
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
72 PLDkit's breakout board.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
73
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
74 This current solution is much better than manually connecting each wire
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
75 individually: with connectors being solid pieces rather than individual wires,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
76 a setup can be very easily taken down and then put back together, which is
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
77 absolutely essential for our mode of usage. But the downside of this approach
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
78 is that once our two 15-position female connectors mate with PLDkit's headers,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
79 there is no way to make a separate connection to other signals which are not
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
80 covered by our basic 10-wire set. This limitation is becoming problematic for
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
81 two reasons:
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
82
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
83 1) Our upcoming Caramel2 board will have the same 10-pin DUART header as FCDEV3B
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
84 and MMTB1 (with DCD & DTR present like on MMTB1), but it will also have an
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
85 additional RI modem control output on another Calypso GPIO accessible on the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
86 general expansion interface header. There is no room to squeeze this extra RI
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
87 signal into our standardized 10-pin DUART interface, but this extra signal is
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
88 rarely needed. The compromise solution currently being pursued is that the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
89 main 10-wire ribbon will connect all UART signals (both UARTs) with the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
90 exception of RI, and those who need RI should be able to connect it with a
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
91 separate individual wire, connecting to the GPIO1 pin on the general expansion
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
92 interface header on the Caramel2 side. But if we use PLDkit breakout boards
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
93 with our current ribbon cables with crimp terminations, there will be no way to
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
94 connect this extra RI wire to the FT2232D adapter board when the big 15-pin
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
95 connector blocks the entire header.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
97 2) PLDkit's FT2232D breakout boards bring out USB 5V on one of their pins, and
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
98 this auxiliary 5V output is useful in some applications. We have one upcoming
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
99 application where this auxiliary 5V will be used to exercise the Calypso+Iota
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
100 chipset's VCHG boot mode, also on the upcoming Caramel2 board - but we get into
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
101 the same problem of the PLDkit board header pin becoming inaccessible when our
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
102 crimp-terminated ribbon cables are used.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
103
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
104 If we replace the generic PLDkit breakout with our own custom FreeCalypso USB
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
105 to dual UART adapter board, we can easily solve these problems by implementing
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 our own custom header pinouts. The new DUART28 adapter board covered by the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 present design spec will bring out 3 headers as follows:
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
108
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
109 * One 10-pin header carrying TxD, RxD, RTS, CTS, DTR and DCD for UART 0 and
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
110 just TxD & RxD for UART 1, in a pinout exactly matching our standardized
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 FreeCalypso DUART interface;
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 * One 3-pin header carrying UART 0 auxiliary modem control inputs DSR and RI,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 plus a ground pin;
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 * One 2-pin header bringing out USB 5V and GND, for auxiliary uses.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118 1.2. 3.3V vs. 2.8V logic levels
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 Calypso I/O pins have native 2.8V logic levels, but they are specified as being
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 tolerant of 3.3V. They do have internal clamping diodes to the Calypso chip's
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 2.8V V-IO rail, but their forward drop voltage is right around 0.5 V, thus if
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 external inputs are at 0.5 V above V-IO (practically meaning 3.3V inputs), no
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 significant current flows through these clamping diodes.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 When we use a raw FT2232D breakout board as our USB to FreeCalypso DUART
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 adapter, we are connecting the FT2232D chip's 3.3V outputs directly to Calypso
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 inputs; this arrangement has been working well for us since 2017, but a more
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 proper 2.8V DUART adapter is desirable for a few reasons:
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 * When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO
35
846ebd21db8e duart28/design-spec: minor fixes in the so-far-written section
Mychaela Falconia <falcon@freecalypso.org>
parents: 34
diff changeset
133 regulator (the one that produces the 2.8V V-IO rail) switches into sleep mode,
34
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 which has much looser regulation than in the regular Active mode. In this
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 condition external 3.3V can feed into the V-IO rail through pull-up resistors
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 and pull the rail itself a little higher than where the chipset's own regulators
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 would have it, which is certainly not desirable. If UART inputs to the Calypso
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 board are driven with 2.8V logic levels rather than 3.3V, this problem is not
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 expected to occur.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 * If we are going to build a custom FreeCalypso DUART adapter for other reasons,
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 it is only proper to make it 2.8V native rather than 3.3V - after all, our
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 adapter is highly specific to Calypso applications, not generic, and Calypso
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 has native 2.8V I/O.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 * We have a competitor: Sysmocom folks use CP2105 adapters (mv-uart adapter
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 board and other integrated designs) instead of our FT2232D, and their
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 CP2105-based designs operate at native 2.8V logic levels, no 3.3V. For
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 political reasons it is important to be no worse than the competition, giving
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 us one more reason to go for native 2.8V.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 Because FT2232D I/O (unlike CP2105, FT232R and many other chips that aren't
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 suitable for other reasons) cannot go below 3.3V, making an FT2232D-based
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 adapter put out 2.8V logic levels requires inserting an extra level shifter
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 after FT2232D outputs - we shall use an LVC buffer for this purpose.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 1.3. Partial power-down considerations
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 The following two corner cases need to be considered, as each can be a trouble
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 spot:
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 1) When the USB to DUART adapter is connected to a host computer and thus has
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 USB power present, but the connected Calypso device is in the switched-off
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 state in the Iota VRPC sense (a condition that occurs all the time in normal
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 operation, e.g., whenever you are running fc-loadtool and waiting to press the
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 PWON button on the board), current can flow from USB DUART adapter outputs into
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 powered-down Calypso chip inputs. This current flow cannot be eliminated
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 without putting LVC or similar buffers on the Calypso board side, but we need
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 to be mindful of this current and we need to limit it.
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 2) When a Calypso device is connected to the USB DUART adapter, the Calypso
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 device is up and running (VRPC Active state), but there is no USB host
35
846ebd21db8e duart28/design-spec: minor fixes in the so-far-written section
Mychaela Falconia <falcon@freecalypso.org>
parents: 34
diff changeset
173 connected, current can flow from Calypso outputs into a powered-down FT2232D
846ebd21db8e duart28/design-spec: minor fixes in the so-far-written section
Mychaela Falconia <falcon@freecalypso.org>
parents: 34
diff changeset
174 (or other front-end chips) in the USB DUART adapter. With our current raw
37
b2d6d8f756ea duart28/design-spec: re-measured partial power-down current
Mychaela Falconia <falcon@freecalypso.org>
parents: 36
diff changeset
175 FT2232D-to-Calypso arrangement we have about 5.8 mA of current flowing per pin
b2d6d8f756ea duart28/design-spec: re-measured partial power-down current
Mychaela Falconia <falcon@freecalypso.org>
parents: 36
diff changeset
176 under the described condition, which is way too much.
34
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 If we replace the generic FT2232D breakout with our own custom adapter board
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 design, we can solve the second partial power-down problem (the case of Calypso
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 on, but no USB host) by inserting LVC buffers in front of FT2232D inputs -
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 these LVC buffers are fully specified for partial power-down applications and
0eca5449abd7 duart28/design-spec started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 have very small Ioff leakage current.
36
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
183
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
184 2. Circuit design
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
185
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
186 2.1. FT2232D core section
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
187
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
188 Our FT2232D core section (basically everything from the USB connector to the
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
189 FT2232D chip's ADBUS and BDBUS interfaces) is based on PLDkit's generic FT2232D
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
190 module:
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
191
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
192 ftp://ftp.freecalypso.org/pub/USB/FTDI/FT2232D_module_B_schematics.pdf
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
193
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
194 This core section is essentially boilerplate in which we have zero desire for
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
195 innovation, hence we would like to copy it from a known-working design. In
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
196 this project the section in question has been recaptured in our ueda language
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
197 based on the above schematic drawing.
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
198
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
199 2.2. UART outputs from the adapter
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
200
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
201 We have a total of 4 outputs: TxD, RTS, DTR and TxD2. Because we wish to put
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
202 out 2.8V logic levels rather than 3.3V, each output needs to pass through an
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
203 LVC buffer; we use a 74LVC541A as our buffer IC.
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
204
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
205 There is also a series resistor inserted into each output after the LVC buffer;
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
206 the initial value to be populated on the first board build is 2.2 kOhm, to be
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
207 further tuned empirically. The purpose of these series resistors is to limit
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
208 the current that will flow from our DUART28 adapter into the Calypso target
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
209 when the Calypso is powered down - see section 1.3. In our current setup with
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
210 direct FT2232D to Calypso connection (no series resistors) this current has
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
211 been measured to be somewhere around 1.77 mA, and it appears to be limited by
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
212 the current sourcing ability of FT2232D drivers (1 mA per datasheet). However,
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
213 our new LVC buffers have much stronger drivers, specified to both source and
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
214 sink up to 24 mA, thus series resistors become mandatory for proper operation
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
215 in this partial power-down scenario.
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
216
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
217 The value of these series resistors is a delicate tuning job: they need to be
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
218 large enough to limit current flow in the partial power-down scenario, but they
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
219 cannot be too large, or they will adversely affect serial communication. Each
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
220 of these series resistors will form an RC circuit together with various
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
221 parasitic capacitances on the Calypso target side; larger R translates to a
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
222 larger RC time constant, resulting in slower signal rise and fall times,
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
223 adversely affecting serial communication at higher baud rates.
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
224
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
225 We have an existing Calypso development board produced by another company that
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
226 features old-fashioned RS-232 interfaces (classic DE9F connectors) and uses an
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
227 on-board RS-232 to LVTTL/LVCMOS converter; this board features 1 kOhm series
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
228 resistors in the same place as in our proposed design, and it works fine at
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
229 812500 baud. If we populate the same 1 kOhm resistors, the undesirable current
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
230 in the partial power-down scenario will be 2.8 mA per pin, which is greater
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
231 than our current 1.77 mA; with our current plan of populating 2.2 kOhm resistors
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
232 the current will be 1.27 mA, and we are hoping that 812500 baud communication
40e2106a0500 duart28/design-spec: coming along
Mychaela Falconia <falcon@freecalypso.org>
parents: 35
diff changeset
233 will still work OK.
38
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
234
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
235 2.3. UART inputs to the adapter
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
236
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
237 We have a total of 6 inputs: RxD, CTS, DSR, DCD, RI and RxD2. These inputs
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
238 need to pass through LVC buffers just like the outputs, but for a different
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
239 reason. With inputs there is no need for voltage level translation, but the
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
240 need for LVC buffers arises because of partial power-down considerations - the
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
241 scenario when the Calypso board is fully up and running and is connected to the
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
242 DUART adapter, but there is no USB host connected - see section 1.3. If
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
243 Calypso UART outputs are connected directly to FT2232D inputs without any
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
244 intermediate buffers, this condition is handled very poorly, with about 5.8 mA
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
245 of current flowing per pin, which is certainly not acceptable for a proper
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
246 design.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
247
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
248 Insertion of an LVC buffer into each input signal path neatly solves this
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
249 problem: these buffers are specifically designed for partial power-down
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
250 applications and have very small Ioff leakage current - listed as 0.1 uA
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
251 typical or 10 uA maximum in the 74LVC541A datasheet.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
252
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
253 One additional complication is that we also have to add explicit pull-up
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
254 resistors (to our local 2.8V rail) on each of our 6 inputs in front of the
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
255 buffer IC. Many of our UART inputs may be legitimately left unconnected, and
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
256 these unconnected inputs should be sensed by our FT2232D USB UART as high. If
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
257 we were connecting to FT2232D inputs directly, the FT2232D chip's internal
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
258 pull-ups would take care of this condition, but when we have a 74LVC541A buffer
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
259 in front of these FT2232D inputs, this buffer IC's own inputs must not be left
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
260 floating.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
261
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
262 2.4. LVC buffer details
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
263
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
264 We shall use two LVC buffer ICs of the same type (74LVC541A), one for the 4
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
265 outputs, the other for the 6 inputs. Each 74LVC541A is an octal buffer, thus
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
266 some slots in each IC remain unused; all unused slots will have their A inputs
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
267 tied to GND. Both nOE1 and nOE2 on each buffer IC are also tied to GND,
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
268 resulting in all buffers being always enabled.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
269
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
270 The 74LVC541A buffer for outputs will have its Vcc supply pin fed with 2.8V, as
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
271 required in order to produce 2.8V logic levels on outputs from the adapter.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
272 However, the other 74LVC541A buffer for inputs will have its Vcc supply pin fed
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
273 with 3.3V, same as FT2232D VCCIOA and VCCIOB.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
274
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
275 When the inputs coming from the connected Calypso target have 2.8V logic levels
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
276 and ultimately need to go to FT2232D receivers operating at 3.3V, a sort of
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
277 translation will have to happen somewhere, with a CMOS input structure operating
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
278 with a 3.3V supply being fed 2.8V inputs. We can make this translation happen
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
279 in the FT2232D if we use an intermediate LVC buffer powered at 2.8V or no
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
280 intermediate buffer at all, or we can make this translation happen in the LVC
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
281 buffer if the latter is powered with the same 3.3V as the FT2232D I/O pins.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
282 The second approach has been chosen because the behaviour of 74LVC541A under
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
283 these conditions is much better understood than the behaviour of FT2232D I/O
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
284 cells under the same, thanks to much better documentation being available for
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
285 74LVC541A than for that part of FT2232D.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
286
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
287 Please note, however, that the pull-up resistors on inputs before input-serving
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
288 74LVC541A buffer will be wired to our local 2.8V rail, not to 3.3V, even though
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
289 the buffer IC will be powered with 3.3V. This way all interface signals exist
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
290 strictly in the 2.8V domain and never get exposed to 3.3V in any form.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
291
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
292 2.5. LDO regulators
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
293
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
294 Two LDO regulators will be implemented on our adapter board, both powered from
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
295 USB 5V: one producing 3.3V, the other producing 2.8V. Our 3.3V LDO will power
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
296 FT2232D VCCIOA & VCCIOB and the input-serving 74LVC541A buffer, whereas the
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
297 other 2.8V LDO will power our output-serving 74LVC541A buffer and our input
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
298 pull-up resistors. Both LDOs will be of TLV702 family from TI, based on our
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
299 recent good experiences with this LDO family in other projects.
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
300
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
301 The FT2232D chip's built-in 3.3V LDO won't be used: its 5 mA current limit
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
302 seems to be too small, and our current FT2232D adapter boards made by PLDkit
ba83a7cd6451 duart28/design-spec: circuit description should be complete
Mychaela Falconia <falcon@freecalypso.org>
parents: 37
diff changeset
303 don't use it either, using an external beefier LDO instead.
41
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
304
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
305 3. PCB layout specification
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
306
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
307 3.1. Overall dimensions
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
308
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
309 The generic FT2232D breakout board from PLDkit which the present DUART28 seeks
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
310 to replace measures 39.37x46.99 mm or 1550x1850 mil. If the present DUART28
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
311 circuit can be squeezed into the same size, great - but such squeeze is NOT
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
312 required. If our DUART28 requires a larger PCB because of our greater circuit
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
313 complexity and having more components, using a larger PCB would be perfectly
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
314 fine - however much space is needed to get the job done. There is no specific
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
315 form factor requirement, i.e., this project is a free-form design.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
316
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
317 3.2. Layer count
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
318
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
319 PLDkit's FT2232D adapter board appears to have a 2-layer PCB, and our competitor
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
320 mv-uart by Sysmocom (CP2105-based) is known to have a 2-layer PCB thanks to
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
321 published design files. However, we shall go by the same business logic as with
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
322 board dimensions: if the needed layout can be done in just 2 layers, great, but
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
323 if the PCB layout engineer feels that going to 4 layers would be better or would
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
324 make the layout job easier, it would be perfectly OK to have 4 layers.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
325
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
326 3.3. Mounting holes
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
327
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
328 The PCB should have 4 mounting holes in the corners, accommodating M3 screws.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
329 It is OK to increase overall board dimensions slightly to make room for these
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
330 mounting holes.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
331
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
332 3.4. Placement of connectors
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
333
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
334 USB mini-B connector J1 must be placed along one of the board edges; it does not
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
335 matter along which edge, or exactly where.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
336
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
337 Shrouded 2x5 header J2 can be placed anywhere, as long as the placement makes
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
338 sense for cable attachment purposes. The cable plugged into this connector will
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
339 be a 10-wire ribbon terminated with an IDC connector, thus the body of the flat
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
340 cable will lie parallel to the board surface. Orientation: the body of the
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
341 cable will face toward the even-numbered row of pins, i.e., away from the
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
342 polarizing tab identified with a silk screen mark in the currently drawn
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
343 footprint.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
344
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
345 Little headers J3 and J4 can be placed anywhere; they are not shrouded and the
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
346 only things that can be connected to them are either individual jumper wires or
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
347 crimped assemblies with wires rising up, perpendicular to the board.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
348
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
349 3.5. Connector silk screen labels
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
350
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
351 All three user connection headers J2, J3 and J4 shall have silk screen labels
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
352 identifying every pin. J2 pins shall be labeled as follows, numbers in the
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
353 middle indicate physical pins and shall NOT be placed on the silk screen
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
354 themselves:
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
355
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
356 GND 1 2 GND
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
357 RxD2 3 4 RxD
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
358 TxD2 5 6 TxD
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
359 DCD 7 8 CTS
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
360 DTR 9 10 RTS
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
361
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
362 J3 pins shall be labeled as follows, numbers on the left indicate physical pins
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
363 and shall NOT be placed on the silk screen themselves:
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
364
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
365 1 GND
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
366 2 DSR
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
367 3 RI
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
368
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
369 J4 pins shall be labeled as follows, same deal with pin numbers:
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
370
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
371 1 +5V
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
372 2 GND
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
373
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
374 3.6. 74LVC541A slot assignment
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
375
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
376 74LVC541A is an octal buffer IC that can be seen as a bundle of 8 single buffers
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
377 with common output enables; the latter are always enabled in our present
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
378 circuit. The present design uses two of these octal buffer ICs (see section
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
379 2.4): one with 4 signals and 4 unused slots (grounded A inputs, unconnected Y
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
380 outputs) and one with 6 signals and 2 unused slots. The mapping of which signal
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
381 should go to which An/Yn slot is arbitrary from the standpoint of circuit
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
382 functionality, thus this mapping should be made at the time of PCB layout for
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
383 physical layout optimization.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
384
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
385 The mapping of signals to U5 and U6 slots is defined in U5.slotmap and
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
386 U6.slotmap text files; to change these mappings, edit the two files to define
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
387 the desired mapping, then recompile the netlist by running 'make', producing an
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
388 updated pcb-netlist.txt generated file.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
389
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
390 The preliminary slot mapping that exists in the present netlist was created as
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
391 a placeholder to pass compilation, and is NOT expected to be anywhere close to
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
392 optimal for layout! Therefore, the PCB layout engineer is expected to review
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
393 this slot mapping and optimize it for layout.
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
394
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
395 3.7. Power bypass capacitors
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
396
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
397 By the very nature of power bypass capacitors, a netlist gives absolutely no
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
398 indication as to where they need to be placed - yet their physical placement is
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
399 essential to their circuit function. Because the design of this board is
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
400 captured in ueda language instead of graphical schematics, it is possible that
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
401 the PCB layout engineer may have some difficulty with reading our ueda design
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
402 source to understand the design intent as to where each bypass capacitor should
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
403 be placed. The following listing is intended to resolve this ambiguity:
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
404
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
405 * C4 and C7 need to be placed at the output of L1 on the P_5V net;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
406 * C8 needs to be placed at the input of LDO regulator U3;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
407 * C9 needs to be placed at the output of LDO regulator U3;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
408 * C10 needs to be placed at the input of LDO regulator U4;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
409 * C11 needs to be placed at the output of LDO regulator U4;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
410 * C12 needs to be placed near pin 20 (Vcc) of U5;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
411 * C13 needs to be placed near pin 20 (Vcc) of U6;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
412 * C14 needs to be placed near pin 14 (VCCIOA) of U1;
45bbb72a8916 duart28/design-spec: layout instructions added
Mychaela Falconia <falcon@freecalypso.org>
parents: 38
diff changeset
413 * C15 needs to be placed near pin 31 (VCCIOB) of U1.