FreeCalypso > hg > fc-small-hw
annotate duart28/src/vsrc/eeprom_93Cx6_16bit.v @ 29:ccb544045646
duart28: U5 & U6 preliminary slotmaps
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 29 Jun 2020 03:15:08 +0000 |
parents | 22aba3a61a4b |
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rev | line source |
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22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 module eeprom_93Cx6_16bit (GND, VCC, CS, SK, DIN, DOUT); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 input GND, VCC; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 input CS, SK, DIN; |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 output DOUT; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 /* instantiate the package; the mapping of signals to pins is defined here */ |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 pkg_8pin pkg (.pin_1(CS), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 .pin_2(SK), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 .pin_3(DIN), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 .pin_4(DOUT), |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 .pin_5(GND), |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 .pin_6(VCC), /* ORG input on some 93Cx6 variants */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 .pin_7(), /* no connect */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 .pin_8(VCC) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 ); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 endmodule |