FreeCalypso > hg > fc-small-hw
annotate duart28/src/vsrc/regulator_with_caps.v @ 49:d4da3aed4c1e
duart28c/src/primitives: OD buffer pieces added
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 29 Jul 2020 07:30:45 +0000 |
parents | 22aba3a61a4b |
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rev | line source |
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22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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1 module regulator_with_caps (GND, IN, OUT); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 input GND, IN; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 output OUT; |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 regulator_ic reg (.IN(IN), |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 .OUT(OUT), |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 .GND(GND), |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 .EN(IN) |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 ); |
22aba3a61a4b
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 capacitor input_cap (IN, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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13 capacitor output_cap (OUT, GND); |
22aba3a61a4b
duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 endmodule |