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annotate lunalcd2/src/Makefile @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents
children 38c713964bb7
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59
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 vsrc/current_select.v vsrc/lcd_module.v
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 NETS= sverp.unet
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 all: ${NETS}
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 sverp.unet: ${VSRCS} primitives Makefile
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 ueda-sverp -o $@ ${VSRCS}
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 clean:
d5d14b426faa lunalcd2: structural Verilog source captured
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 rm -f *.unet *.txt *.csv errs elements.pcb