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annotate mmtb1/schem+bom/vsrc/board.v @ 61:df8f40386c0b

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lunalcd2/src/Makefile: generate pcb-netlist.txt
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 19:08:13 +0000
parents 0f9bdd60ce50
children
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1 /*
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2 * This is the top level structural Verilog module for the MMTB1 board.
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3 */
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4
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5 module board ();
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6
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7 wire GND, VBAT, Vio;
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8 wire PWON, nTESTRESET;
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9
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10 wire TX_IRDA, RX_IRDA;
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11 wire TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM;
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12 wire GPIO2_DCD, GPIO3_DTR;
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13
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14 wire VSIM, SIM_CLK, SIM_RST, SIM_IO;
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15
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16 wire EARP, EARN, MICP, MICN;
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17
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18 /* power input to the rig */
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19 conn_3pin pwr_input_conn (.pin_1(VBAT),
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20 .pin_2(),
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21 .pin_3(GND)
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22 );
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23
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24 capacitor big_cap (VBAT, GND);
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25
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26 /* DUT interface connector */
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27 interface dut_if (.GND(GND),
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28 .VBAT(VBAT),
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29 .PWON(PWON),
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30 .nTESTRESET(nTESTRESET),
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31 .Vio(Vio),
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32 .TX_IRDA(TX_IRDA),
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33 .RX_IRDA(RX_IRDA),
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34 .TX_MODEM(TX_MODEM),
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35 .RX_MODEM(RX_MODEM),
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36 .RTS_MODEM(RTS_MODEM),
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37 .CTS_MODEM(CTS_MODEM),
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38 .GPIO2_DCD(GPIO2_DCD),
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39 .GPIO3_DTR(GPIO3_DTR),
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40 .VSIM(VSIM),
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41 .SIM_IO(SIM_IO),
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42 .SIM_CLK(SIM_CLK),
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43 .SIM_RST(SIM_RST),
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44 .EARP(EARP),
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45 .EARN(EARN),
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46 .MICP(MICP),
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47 .MICN(MICN)
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48 );
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49
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50 /* PWON and nTESTRESET pushbuttons */
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51 pushbutton_wrap pwr_btn (PWON, GND);
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52 pushbutton_wrap reset_btn (nTESTRESET, GND);
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53
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54 /* power on LED */
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55 led_circuit led (.GND(GND),
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56 .VBAT(VBAT),
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57 .Signal(Vio)
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58 );
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59
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60 /* SIM socket */
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61 sim_socket_block sim (.GND(GND),
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62 .VSIM(VSIM),
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63 .SIM_CLK(SIM_CLK),
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64 .SIM_RST(SIM_RST),
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65 .SIM_IO(SIM_IO)
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66 );
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67
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68 /* UART interfaces */
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69 uart_bringout uart_if (.GND(GND),
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70 .TX_MODEM(TX_MODEM),
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71 .RX_MODEM(RX_MODEM),
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72 .RTS_MODEM(RTS_MODEM),
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73 .CTS_MODEM(CTS_MODEM),
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74 .GPIO_DCD(GPIO2_DCD),
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75 .GPIO_DTR(GPIO3_DTR),
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76 .TX_IRDA(TX_IRDA),
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77 .RX_IRDA(RX_IRDA)
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78 );
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79
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80 /* earpiece and microphone connectors */
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81 header_2pin J5 (EARP, EARN);
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82 header_2pin J6 (MICP, MICN);
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83
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84 endmodule