FreeCalypso > hg > fc-small-hw

annotate lunalcd1/src/regulator.v @ 11:e4f0ea46183a

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd1.pcb: should be complete
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Apr 2020 23:26:47 +0000
parents 839e9b527e69
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
5
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 module regulator (IN, OUT, GND, EN);
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 input IN, GND, EN;
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 output OUT;
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 pkg_5pin pkg ( .pin_1(IN),
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 .pin_2(GND),
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 .pin_3(EN),
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 .pin_4(), /* no connect */
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 .pin_5(OUT)
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 );
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12
839e9b527e69 lunalcd1 board project started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 endmodule