FreeCalypso > hg > fc-small-hw
annotate lunalcd1/src/schem.v @ 10:f8735d13a3ea
lunalcd1.pcb: layout started, close to complete
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Apr 2020 22:41:19 +0000 |
parents | 28a0574af823 |
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rev | line source |
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5
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1 module board (); |
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2 |
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3 wire GND, VBAT, Vio; |
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4 wire [15:0] DB; |
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5 wire RD, WR, RS, CS, RESET; |
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6 wire BL_EN, Vbacklight; |
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7 wire [1:3] LEDK; |
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8 |
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9 /* LCD module connector */ |
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10 |
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11 conn_36pin_plus2 fpc ( .pin_1(DB[15]), |
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12 .pin_2(DB[14]), |
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13 .pin_3(DB[13]), |
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14 .pin_4(DB[12]), |
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15 .pin_5(DB[11]), |
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16 .pin_6(DB[10]), |
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17 .pin_7(DB[9]), |
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18 .pin_8(DB[8]), |
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19 .pin_9(GND), |
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20 .pin_10(DB[7]), |
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21 .pin_11(DB[6]), |
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22 .pin_12(DB[5]), |
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23 .pin_13(DB[4]), |
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24 .pin_14(DB[3]), |
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25 .pin_15(DB[2]), |
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26 .pin_16(DB[1]), |
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27 .pin_17(DB[0]), |
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28 .pin_18(Vio), /* IOVCC */ |
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29 .pin_19(Vio), /* VCI */ |
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30 .pin_20(RD), |
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31 .pin_21(WR), |
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32 .pin_22(RS), |
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33 .pin_23(CS), |
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34 .pin_24(RESET), |
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35 .pin_25(GND), /* IM0 tied low */ |
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36 .pin_26(GND), |
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37 .pin_27(Vbacklight), /* LEDA */ |
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38 .pin_28(LEDK[1]), |
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39 .pin_29(LEDK[2]), |
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40 .pin_30(LEDK[3]), |
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41 /* the remaining pins are NC */ |
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42 .pin_31(), |
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43 .pin_32(), |
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44 .pin_33(), |
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45 .pin_34(), |
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46 .pin_35(), |
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47 .pin_36(), |
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48 /* ground the two mounting pads */ |
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49 .pin_37(GND), |
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50 .pin_38(GND) |
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51 ); |
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52 |
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53 /* bypass cap for LCD module core */ |
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54 capacitor LCD_bypass_cap (Vio, GND); |
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55 |
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56 /* main interface connector */ |
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57 |
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58 header_26pin main_if ( .pin_1(DB[15]), |
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59 .pin_2(DB[14]), |
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60 .pin_3(DB[13]), |
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61 .pin_4(DB[12]), |
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62 .pin_5(DB[11]), |
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63 .pin_6(DB[10]), |
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64 .pin_7(DB[9]), |
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65 .pin_8(DB[8]), |
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66 .pin_9(DB[7]), |
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67 .pin_10(DB[6]), |
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68 .pin_11(DB[5]), |
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69 .pin_12(DB[4]), |
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70 .pin_13(DB[3]), |
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71 .pin_14(DB[2]), |
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72 .pin_15(DB[1]), |
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73 .pin_16(DB[0]), |
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74 .pin_17(CS), |
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75 .pin_18(RD), |
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76 .pin_19(WR), |
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77 .pin_20(RS), |
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78 .pin_21(GND), |
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79 .pin_22(GND), |
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80 .pin_23(RESET), |
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81 .pin_24(Vio), |
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82 .pin_25(BL_EN), |
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83 .pin_26(GND) |
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84 ); |
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85 |
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86 /* backlight circuit */ |
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87 |
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88 header_2pin VBAT_conn ( .pin_1(VBAT), |
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89 .pin_2(GND) |
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90 ); |
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91 |
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92 capacitor VBAT_bypass_cap (VBAT, GND); |
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93 |
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94 regulator reg ( .IN(VBAT), |
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95 .OUT(Vbacklight), |
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96 .GND(GND), |
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97 .EN(BL_EN) |
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98 ); |
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99 |
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100 capacitor reg_out_cap (Vbacklight, GND); |
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101 |
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102 resistor R1 (LEDK[1], GND); |
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103 resistor R2 (LEDK[2], GND); |
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104 resistor R3 (LEDK[3], GND); |
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105 |
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106 resistor R4 (BL_EN, GND); |
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5
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107 |
5
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108 endmodule |