FreeCalypso > hg > fc-small-hw

annotate duart28/src/vsrc/eeprom_93Cx6_16bit.v @ 84:dbd57e8dd82a default tip

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
sim-fpc-pasv/pcb: add Makefile for Gerber output
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 02 Nov 2022 07:22:44 +0000
parents 22aba3a61a4b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 module eeprom_93Cx6_16bit (GND, VCC, CS, SK, DIN, DOUT);
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 input GND, VCC;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 input CS, SK, DIN;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 output DOUT;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 /* instantiate the package; the mapping of signals to pins is defined here */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 pkg_8pin pkg (.pin_1(CS),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 .pin_2(SK),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 .pin_3(DIN),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 .pin_4(DOUT),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 .pin_5(GND),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 .pin_6(VCC), /* ORG input on some 93Cx6 variants */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 .pin_7(), /* no connect */
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 .pin_8(VCC)
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17 );
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 endmodule