FreeCalypso > hg > fc-small-hw

annotate duart28/src/vsrc/regulator_with_caps.v @ 84:dbd57e8dd82a default tip

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
sim-fpc-pasv/pcb: add Makefile for Gerber output
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 02 Nov 2022 07:22:44 +0000
parents 22aba3a61a4b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
23
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 module regulator_with_caps (GND, IN, OUT);
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 input GND, IN;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 output OUT;
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6 regulator_ic reg (.IN(IN),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 .OUT(OUT),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 .GND(GND),
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9 .EN(IN)
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 );
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 capacitor input_cap (IN, GND);
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 capacitor output_cap (OUT, GND);
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
22aba3a61a4b duart28: vsrc passes sverp
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 endmodule