comparison lunalcd2/src/Makefile @ 70:000411b39576

lunalcd2/src/Makefile: generate BOM outputs
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 26 Jun 2021 21:16:48 +0000
parents 907bff95244d
children
comparison
equal deleted inserted replaced
69:fa13dce94843 70:000411b39576
1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \ 1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
2 vsrc/current_select.v vsrc/lcd_module.v 2 vsrc/current_select.v vsrc/lcd_module.v
3 BOMS= tallied-bom.txt tallied-bom.csv comptab.txt
3 NETS= sverp.unet bound.unet pcb-netlist.txt 4 NETS= sverp.unet bound.unet pcb-netlist.txt
4 5
5 all: ${NETS} elements.pcb 6 all: ${BOMS} ${NETS} elements.pcb
7
8 tallied-bom.txt: MCL
9 ueda-mkbom -cr > $@
10
11 tallied-bom.csv: MCL
12 ueda-csvbom > $@
13
14 comptab.txt: MCL
15 ueda-shortbom > $@
6 16
7 sverp.unet: ${VSRCS} primitives Makefile 17 sverp.unet: ${VSRCS} primitives Makefile
8 ueda-sverp -o $@ ${VSRCS} 18 ueda-sverp -o $@ ${VSRCS}
9 19
10 bound.unet: MCL sverp.unet 20 bound.unet: MCL sverp.unet