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duart28/design-spec started
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 14 Jul 2020 07:40:42 +0000
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children 846ebd21db8e
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33:0073141010a2 34:0eca5449abd7
1 FreeCalypso DUART28 Adapter
2 Board design specification
3
4 1. What it is and why it is desired
5
6 Under our FreeCalypso umbrella we have a family of hardware products based on
7 the Calypso chipset from Texas Instruments. The Calypso chip has two UARTs,
8 one with TxD & RxD data leads plus RTS & CTS flow control, and the other with
9 TxD & RxD data leads only. There is also a convention whereby some Calypso
10 GPIOs are defined to be additional modem control signals and associated with
11 the Modem UART (the one that has RTS & CTS flow control in addition to
12 TxD & RxD), thus the result is one UART with a near-complete set of modem
13 control signals and one UART with data leads only.
14
15 The convention established in FreeCalypso is that all of our Calypso development
16 boards bring out both Calypso UARTs in their native form, which is 2.8V native
17 logic levels, tolerant of 3.3V but not any higher voltages. In order to connect
18 these UARTs to a PC or laptop serving as the development host, a separate USB
19 to low-voltage UART adapter board is used, preferably one that puts both UARTs
20 (two ttyUSBx devices) behind a single USB device. Our USB to dual UART
21 converter chip of choice is FT2232D; this chip has been chosen over various
22 competitors because it provides two UART channels (ttyUSBx devices) in one USB
23 device, because it supports non-standard serial baud rates on both channels,
24 allowing us to use GSM-specific high baud rates of 203125, 406250 and 812500
25 bps, and because it supports the full set of modem control signals like one
26 would find on an old-fashioned RS-232 port.
27
28 Since we got our first FCDEV3B boards built in 2017 and up until the present,
29 we've been using FT2232D breakout boards made by PLDkit as our USB to dual UART
30 adapter:
31
32 http://pldkit.com/other/ft2232d-module
33
34 These generic FT2232D adapters work quite well for our current purposes, but
35 now we have several reasons for desiring our own custom-built adapter to
36 replace them, detailed below.
37
38 1.1. Desire for custom interface pinout
39
40 In FreeCalypso we have the following convention: all FC hardware products that
41 bring out both Calypso UARTs do so by way of a single 10-pin (2x5) 2.54 mm
42 header in a fixed pinout given below. This convention was started with
43 FCDEV3B, our first FC hw product, and is now being continued with MMTB1 and
44 Caramel2 boards. Our standardized DUART header pinout is as follows:
45
46 Header pin Calypso signal
47 1 GND
48 2 GND
49 3 TX_IRDA
50 4 TX_MODEM
51 5 RX_IRDA
52 6 RX_MODEM
53 7 GPIO2_DCD
54 8 RTS_MODEM
55 9 GPIO3_DTR
56 10 CTS_MODEM
57
58 Pins 7 and 9 were originally left unused (they are unconnected on FCDEV3B), but
59 they have been assigned as DCD and DTR (from the host's perspective) starting
60 with MMTB1. Note that while DCD and DTR in the table above are named from the
61 host's perspective, all Calypso signals ending with _MODEM or _IRDA are from
62 the chip's perspective, i.e., the opposite.
63
64 When we use FT2232D breakout boards from PLDkit as our USB to DUART adapter, we
65 use a custom hand-made ribbon cable with crimp terminations: a 10-wire ribbon
66 is used, the full ribbon runs intact in the main body of the cable, but toward
67 the FT2232D adapter board the ribbon is split in two, with 7 wires going to the
68 A side of PLDkit's breakout board and with 3 wires going to the B side. Each
69 of the two subribbons (both the 7-wire one and the 3-wire one) gets terminated
70 onto a 15-position female connector, with the two resulting 15-pin connectors
71 mating with the two 15-pin single-row headers located on the two sides of
72 PLDkit's breakout board.
73
74 This current solution is much better than manually connecting each wire
75 individually: with connectors being solid pieces rather than individual wires,
76 a setup can be very easily taken down and then put back together, which is
77 absolutely essential for our mode of usage. But the downside of this approach
78 is that once our two 15-position female connectors mate with PLDkit's headers,
79 there is no way to make a separate connection to other signals which are not
80 covered by our basic 10-wire set. This limitation is becoming problematic for
81 two reasons:
82
83 1) Our upcoming Caramel2 board will have the same 10-pin DUART header as FCDEV3B
84 and MMTB1 (with DCD & DTR present like on MMTB1), but it will also have an
85 additional RI modem control output on another Calypso GPIO accessible on the
86 general expansion interface header. There is no room to squeeze this extra RI
87 signal into our standardized 10-pin DUART interface, but this extra signal is
88 rarely needed. The compromise solution currently being pursued is that the
89 main 10-wire ribbon will connect all UART signals (both UARTs) with the
90 exception of RI, and those who need RI should be able to connect it with a
91 separate individual wire, connecting to the GPIO1 pin on the general expansion
92 interface header on the Caramel2 side. But if we use PLDkit breakout boards
93 with our current ribbon cables with crimp terminations, there will be no way to
94 connect this extra RI wire to the FT2232D adapter board when the big 15-pin
95 connector blocks the entire header.
96
97 2) PLDkit's FT2232D breakout boards bring out USB 5V on one of their pins, and
98 this auxiliary 5V output is useful in some applications. We have one upcoming
99 application where this auxiliary 5V will be used to exercise the Calypso+Iota
100 chipset's VCHG boot mode, also on the upcoming Caramel2 board - but we get into
101 the same problem of the PLDkit board header pin becoming inaccessible when our
102 crimp-terminated ribbon cables are used.
103
104 If we replace the generic PLDkit breakout with our own custom FreeCalypso USB
105 to dual UART adapter board, we can easily solve these problems by implementing
106 our own custom header pinouts. The new DUART28 adapter board covered by the
107 present design spec will bring out 3 headers as follows:
108
109 * One 10-pin header carrying TxD, RxD, RTS, CTS, DTR and DCD for UART 0 and
110 just TxD & RxD for UART 1, in a pinout exactly matching our standardized
111 FreeCalypso DUART interface;
112
113 * One 3-pin header carrying UART 0 auxiliary modem control inputs DSR and RI,
114 plus a ground pin;
115
116 * One 2-pin header bringing out USB 5V and GND, for auxiliary uses.
117
118 1.2. 3.3V vs. 2.8V logic levels
119
120 Calypso I/O pins have native 2.8V logic levels, but they are specified as being
121 tolerant of 3.3V. They do have internal clamping diodes to the Calypso chip's
122 2.8V V-IO rail, but their forward drop voltage is right around 0.5 V, thus if
123 external inputs are at 0.5 V above V-IO (practically meaning 3.3V inputs), no
124 significant current flows through these clamping diodes.
125
126 When we use a raw FT2232D breakout board as our USB to FreeCalypso DUART
127 adapter, we are connecting the FT2232D chip's 3.3V outputs directly to Calypso
128 inputs; this arrangement has been working well for us since 2017, but a more
129 proper 2.8V DUART adapter is desirable for a few reasons:
130
131 * When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for
132 Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO
133 regulator (the one that produces the 2.8V V-IO raill) switches into sleep mode,
134 which has much looser regulation than in the regular Active mode. In this
135 condition external 3.3V can feed into the V-IO rail through pull-up resistors
136 and pull the rail itself a little higher than where the chipset's own regulators
137 would have it, which is certainly not desirable. If UART inputs to the Calypso
138 board are driven with 2.8V logic levels rather than 3.3V, this problem is not
139 expected to occur.
140
141 * If we are going to build a custom FreeCalypso DUART adapter for other reasons,
142 it is only proper to make it 2.8V native rather than 3.3V - after all, our
143 adapter is highly specific to Calypso applications, not generic, and Calypso
144 has native 2.8V I/O.
145
146 * We have a competitor: Sysmocom folks use CP2105 adapters (mv-uart adapter
147 board and other integrated designs) instead of our FT2232D, and their
148 CP2105-based designs operate at native 2.8V logic levels, no 3.3V. For
149 political reasons it is important to be no worse than the competition, giving
150 us one more reason to go for native 2.8V.
151
152 Because FT2232D I/O (unlike CP2105, FT232R and many other chips that aren't
153 suitable for other reasons) cannot go below 3.3V, making an FT2232D-based
154 adapter put out 2.8V logic levels requires inserting an extra level shifter
155 after FT2232D outputs - we shall use an LVC buffer for this purpose.
156
157 1.3. Partial power-down considerations
158
159 The following two corner cases need to be considered, as each can be a trouble
160 spot:
161
162 1) When the USB to DUART adapter is connected to a host computer and thus has
163 USB power present, but the connected Calypso device is in the switched-off
164 state in the Iota VRPC sense (a condition that occurs all the time in normal
165 operation, e.g., whenever you are running fc-loadtool and waiting to press the
166 PWON button on the board), current can flow from USB DUART adapter outputs into
167 powered-down Calypso chip inputs. This current flow cannot be eliminated
168 without putting LVC or similar buffers on the Calypso board side, but we need
169 to be mindful of this current and we need to limit it.
170
171 2) When a Calypso device is connected to the USB DUART adapter, the Calypso
172 device is up and running (VRPC Active state), but there is no USB host
173 connected, current can flow from Calypso outputs into a powered-down FT2232D or
174 other chips in the USB DUART adapter. With our current raw FT2232D-to-Calypso
175 arrangement we have about 5 mA of current flowing per pin under the described
176 condition, which is a little too much.
177
178 If we replace the generic FT2232D breakout with our own custom adapter board
179 design, we can solve the second partial power-down problem (the case of Calypso
180 on, but no USB host) by inserting LVC buffers in front of FT2232D inputs -
181 these LVC buffers are fully specified for partial power-down applications and
182 have very small Ioff leakage current.