FreeCalypso > hg > fc-small-hw
comparison mmtb1/schem+bom/vsrc/board.v @ 0:0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Mon, 21 Oct 2019 00:53:38 +0000 |
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| children |
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| -1:000000000000 | 0:0f9bdd60ce50 |
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| 1 /* | |
| 2 * This is the top level structural Verilog module for the MMTB1 board. | |
| 3 */ | |
| 4 | |
| 5 module board (); | |
| 6 | |
| 7 wire GND, VBAT, Vio; | |
| 8 wire PWON, nTESTRESET; | |
| 9 | |
| 10 wire TX_IRDA, RX_IRDA; | |
| 11 wire TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM; | |
| 12 wire GPIO2_DCD, GPIO3_DTR; | |
| 13 | |
| 14 wire VSIM, SIM_CLK, SIM_RST, SIM_IO; | |
| 15 | |
| 16 wire EARP, EARN, MICP, MICN; | |
| 17 | |
| 18 /* power input to the rig */ | |
| 19 conn_3pin pwr_input_conn (.pin_1(VBAT), | |
| 20 .pin_2(), | |
| 21 .pin_3(GND) | |
| 22 ); | |
| 23 | |
| 24 capacitor big_cap (VBAT, GND); | |
| 25 | |
| 26 /* DUT interface connector */ | |
| 27 interface dut_if (.GND(GND), | |
| 28 .VBAT(VBAT), | |
| 29 .PWON(PWON), | |
| 30 .nTESTRESET(nTESTRESET), | |
| 31 .Vio(Vio), | |
| 32 .TX_IRDA(TX_IRDA), | |
| 33 .RX_IRDA(RX_IRDA), | |
| 34 .TX_MODEM(TX_MODEM), | |
| 35 .RX_MODEM(RX_MODEM), | |
| 36 .RTS_MODEM(RTS_MODEM), | |
| 37 .CTS_MODEM(CTS_MODEM), | |
| 38 .GPIO2_DCD(GPIO2_DCD), | |
| 39 .GPIO3_DTR(GPIO3_DTR), | |
| 40 .VSIM(VSIM), | |
| 41 .SIM_IO(SIM_IO), | |
| 42 .SIM_CLK(SIM_CLK), | |
| 43 .SIM_RST(SIM_RST), | |
| 44 .EARP(EARP), | |
| 45 .EARN(EARN), | |
| 46 .MICP(MICP), | |
| 47 .MICN(MICN) | |
| 48 ); | |
| 49 | |
| 50 /* PWON and nTESTRESET pushbuttons */ | |
| 51 pushbutton_wrap pwr_btn (PWON, GND); | |
| 52 pushbutton_wrap reset_btn (nTESTRESET, GND); | |
| 53 | |
| 54 /* power on LED */ | |
| 55 led_circuit led (.GND(GND), | |
| 56 .VBAT(VBAT), | |
| 57 .Signal(Vio) | |
| 58 ); | |
| 59 | |
| 60 /* SIM socket */ | |
| 61 sim_socket_block sim (.GND(GND), | |
| 62 .VSIM(VSIM), | |
| 63 .SIM_CLK(SIM_CLK), | |
| 64 .SIM_RST(SIM_RST), | |
| 65 .SIM_IO(SIM_IO) | |
| 66 ); | |
| 67 | |
| 68 /* UART interfaces */ | |
| 69 uart_bringout uart_if (.GND(GND), | |
| 70 .TX_MODEM(TX_MODEM), | |
| 71 .RX_MODEM(RX_MODEM), | |
| 72 .RTS_MODEM(RTS_MODEM), | |
| 73 .CTS_MODEM(CTS_MODEM), | |
| 74 .GPIO_DCD(GPIO2_DCD), | |
| 75 .GPIO_DTR(GPIO3_DTR), | |
| 76 .TX_IRDA(TX_IRDA), | |
| 77 .RX_IRDA(RX_IRDA) | |
| 78 ); | |
| 79 | |
| 80 /* earpiece and microphone connectors */ | |
| 81 header_2pin J5 (EARP, EARN); | |
| 82 header_2pin J6 (MICP, MICN); | |
| 83 | |
| 84 endmodule |