comparison mmtb1/schem+bom/vsrc/uart_bringout.v @ 0:0f9bdd60ce50

fc-small-hw separated from old freecalypso-schem repo
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Oct 2019 00:53:38 +0000
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-1:000000000000 0:0f9bdd60ce50
1 /*
2 * This Verilog module encapsulates the header connector on which
3 * the two Calypso UARTs will be brought out.
4 */
5
6 module uart_bringout (GND, TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM,
7 GPIO_DCD, GPIO_DTR, TX_IRDA, RX_IRDA);
8
9 input GND;
10
11 input TX_MODEM, RTS_MODEM, TX_IRDA, GPIO_DCD;
12 output RX_MODEM, CTS_MODEM, RX_IRDA, GPIO_DTR;
13
14 header_10pin uart_header (.pin_1(GND),
15 .pin_2(GND),
16 .pin_3(TX_IRDA),
17 .pin_4(TX_MODEM),
18 .pin_5(RX_IRDA),
19 .pin_6(RX_MODEM),
20 .pin_7(GPIO_DCD),
21 .pin_8(RTS_MODEM),
22 .pin_9(GPIO_DTR),
23 .pin_10(CTS_MODEM)
24 );
25
26 endmodule