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comparison duart28/src/vsrc/board.v @ 23:22aba3a61a4b

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duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
parents
children 9e71844f4db0
comparison
equal deleted inserted replaced
22:43097651a26d 23:22aba3a61a4b
1 module board ();
2
3 wire GND, P_5V, P_3V3, P_2V8;
4
5 wire [7:0] ADBUS, BDBUS;
6 wire [3:0] ACBUS, BCBUS;
7
8 USB_block usb ( .GND(GND),
9 .P_5V(P_5V),
10 .VCCIOA(P_3V3),
11 .VCCIOB(P_3V3),
12 .ADBUS(ADBUS),
13 .ACBUS(ACBUS),
14 .SI_WUA(P_3V3),
15 .BDBUS(BDBUS),
16 .BCBUS(BCBUS),
17 .SI_WUB(P_3V3),
18 .PWREN() /* no connect */
19 );
20
21 regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3));
22 regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8));
23
24 application_block app ( .GND(GND),
25 .P_2V8(P_2V8),
26 .ADBUS(ADBUS),
27 .BDBUS(BDBUS)
28 );
29
30 endmodule