comparison duart28/src/vsrc/regulator_with_caps.v @ 23:22aba3a61a4b

duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
parents
children
comparison
equal deleted inserted replaced
22:43097651a26d 23:22aba3a61a4b
1 module regulator_with_caps (GND, IN, OUT);
2
3 input GND, IN;
4 output OUT;
5
6 regulator_ic reg (.IN(IN),
7 .OUT(OUT),
8 .GND(GND),
9 .EN(IN)
10 );
11
12 capacitor input_cap (IN, GND);
13 capacitor output_cap (OUT, GND);
14
15 endmodule