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comparison lunalcd1/src/schem.v @ 5:839e9b527e69

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lunalcd1 board project started
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 22 Mar 2020 03:19:38 +0000
parents
children 28a0574af823
comparison
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4:070b11b83958 5:839e9b527e69
1 module board ();
2
3 wire GND, VBAT, Vio;
4 wire [15:0] DB;
5 wire RD, WR, RS, CS, RESET;
6 wire BL_EN, Vbacklight;
7 wire [1:3] LEDK;
8
9 /* LCD module connector */
10
11 conn_36pin_plus2 fpc ( .pin_1(DB[15]),
12 .pin_2(DB[14]),
13 .pin_3(DB[13]),
14 .pin_4(DB[12]),
15 .pin_5(DB[11]),
16 .pin_6(DB[10]),
17 .pin_7(DB[9]),
18 .pin_8(DB[8]),
19 .pin_9(GND),
20 .pin_10(DB[7]),
21 .pin_11(DB[6]),
22 .pin_12(DB[5]),
23 .pin_13(DB[4]),
24 .pin_14(DB[3]),
25 .pin_15(DB[2]),
26 .pin_16(DB[1]),
27 .pin_17(DB[0]),
28 .pin_18(Vio), /* IOVCC */
29 .pin_19(Vio), /* VCI */
30 .pin_20(RD),
31 .pin_21(WR),
32 .pin_22(RS),
33 .pin_23(CS),
34 .pin_24(RESET),
35 .pin_25(GND), /* IM0 tied low */
36 .pin_26(GND),
37 .pin_27(Vbacklight), /* LEDA */
38 .pin_28(LEDK[1]),
39 .pin_29(LEDK[2]),
40 .pin_30(LEDK[3]),
41 /* the remaining pins are NC */
42 .pin_31(),
43 .pin_32(),
44 .pin_33(),
45 .pin_34(),
46 .pin_35(),
47 .pin_36(),
48 /* ground the two mounting pads */
49 .pin_37(GND),
50 .pin_38(GND)
51 );
52
53 /* bypass cap for LCD module core */
54 capacitor LCD_bypass_cap (Vio, GND);
55
56 /* main interface connector */
57
58 header_26pin main_if ( .pin_1(DB[15]),
59 .pin_2(DB[14]),
60 .pin_3(DB[13]),
61 .pin_4(DB[12]),
62 .pin_5(DB[11]),
63 .pin_6(DB[10]),
64 .pin_7(DB[9]),
65 .pin_8(DB[8]),
66 .pin_9(DB[7]),
67 .pin_10(DB[6]),
68 .pin_11(DB[5]),
69 .pin_12(DB[4]),
70 .pin_13(DB[3]),
71 .pin_14(DB[2]),
72 .pin_15(DB[1]),
73 .pin_16(DB[0]),
74 .pin_17(CS),
75 .pin_18(RD),
76 .pin_19(WR),
77 .pin_20(RS),
78 .pin_21(GND),
79 .pin_22(GND),
80 .pin_23(RESET),
81 .pin_24(Vio),
82 .pin_25(BL_EN),
83 .pin_26(GND)
84 );
85
86 /* backlight circuit */
87
88 header_2pin VBAT_conn ( .pin_1(VBAT),
89 .pin_2(GND)
90 );
91
92 capacitor VBAT_bypass_cap (VBAT, GND);
93
94 regulator reg ( .IN(VBAT),
95 .OUT(Vbacklight),
96 .GND(GND),
97 .EN(BL_EN)
98 );
99
100 capacitor reg_out_cap (Vbacklight, GND);
101
102 resistor R1 (LEDK[1], GND);
103 resistor R2 (LEDK[2], GND);
104 resistor R3 (LEDK[3], GND);
105
106 endmodule