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comparison lunalcd2/src/vsrc/board.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents lunalcd1/src/schem.v@28a0574af823
children
comparison
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58:99328e0ff61a 59:d5d14b426faa
1 module board ();
2
3 wire GND, VBAT, Vio, Vio_LCD;
4 wire [15:0] DB;
5 wire RD, WR, RS, CS, RESET;
6 wire BL_EN;
7 wire [1:3] LEDK; /* 1=left, 2=middle, 3=right for layout */
8
9 /* main interface connector */
10
11 header_26pin main_if ( .pin_1(DB[15]),
12 .pin_2(DB[14]),
13 .pin_3(DB[13]),
14 .pin_4(DB[12]),
15 .pin_5(DB[11]),
16 .pin_6(DB[10]),
17 .pin_7(DB[9]),
18 .pin_8(DB[8]),
19 .pin_9(DB[7]),
20 .pin_10(DB[6]),
21 .pin_11(DB[5]),
22 .pin_12(DB[4]),
23 .pin_13(DB[3]),
24 .pin_14(DB[2]),
25 .pin_15(DB[1]),
26 .pin_16(DB[0]),
27 .pin_17(CS),
28 .pin_18(RD),
29 .pin_19(WR),
30 .pin_20(RS),
31 .pin_21(GND),
32 .pin_22(GND),
33 .pin_23(RESET),
34 .pin_24(Vio),
35 .pin_25(BL_EN),
36 .pin_26(GND)
37 );
38
39 resistor BL_EN_pulldown (BL_EN, GND);
40
41 /* backlight power supply */
42
43 header_2pin VBAT_conn ( .pin_1(VBAT),
44 .pin_2(GND)
45 );
46
47 /* LCD module */
48
49 resistor LCD_current_meas (Vio, Vio_LCD);
50
51 capacitor LCD_bypass_cap (Vio_LCD, GND);
52
53 lcd_module lcd (.GND(GND),
54 .VCI(Vio_LCD),
55 .IOVCC(Vio_LCD),
56 .DB(DB),
57 .RD(RD),
58 .WR(WR),
59 .RS(RS),
60 .CS(CS),
61 .RESET(RESET),
62 .IM0(GND),
63 .LEDA(VBAT),
64 /* LEDK order for layout */
65 .LEDK[1](LEDK[3]),
66 .LEDK[2](LEDK[2]),
67 .LEDK[3](LEDK[1])
68 );
69
70 /* MAX1916-based backlight LED current sink */
71
72 bl_current_sink bl_current_sink (.GND(GND),
73 .Vio(Vio),
74 .BL_EN(BL_EN),
75 .LEDK(LEDK)
76 );
77
78 endmodule