diff mmtb1/schem+bom/vsrc/uart_bringout.v @ 0:0f9bdd60ce50

fc-small-hw separated from old freecalypso-schem repo
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 21 Oct 2019 00:53:38 +0000
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmtb1/schem+bom/vsrc/uart_bringout.v	Mon Oct 21 00:53:38 2019 +0000
@@ -0,0 +1,26 @@
+/*
+ * This Verilog module encapsulates the header connector on which
+ * the two Calypso UARTs will be brought out.
+ */
+
+module uart_bringout (GND, TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM,
+		      GPIO_DCD, GPIO_DTR, TX_IRDA, RX_IRDA);
+
+input GND;
+
+input TX_MODEM, RTS_MODEM, TX_IRDA, GPIO_DCD;
+output RX_MODEM, CTS_MODEM, RX_IRDA, GPIO_DTR;
+
+header_10pin uart_header (.pin_1(GND),
+			  .pin_2(GND),
+			  .pin_3(TX_IRDA),
+			  .pin_4(TX_MODEM),
+			  .pin_5(RX_IRDA),
+			  .pin_6(RX_MODEM),
+			  .pin_7(GPIO_DCD),
+			  .pin_8(RTS_MODEM),
+			  .pin_9(GPIO_DTR),
+			  .pin_10(CTS_MODEM)
+	);
+
+endmodule