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diff lunalcd2/src/primitives @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents lunalcd1/src/primitives@839e9b527e69
children
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/primitives	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,16 @@
+/* passives */
+resistor	numpins 2;
+capacitor	numpins 2;
+
+/* LCD module */
+lcd_module_fp	numpins 36;
+
+/* MAX1916 IC */
+pkg_SOT23_6	numpins 6;
+
+/* DIP switch pack */
+pkg_DIP_SW_x4	numpins 8;
+
+/* connectors */
+header_2pin	numpins 2;
+header_26pin	numpins 26;