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diff lunalcd2/src/vsrc/MAX1916.v @ 59:d5d14b426faa

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lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/MAX1916.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,16 @@
+module MAX1916 (GND, EN, SET, LEDK);
+
+input GND, EN, SET;
+output [1:3] LEDK;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_SOT23_6 pkg (.pin_1(EN),
+		 .pin_2(GND),
+		 .pin_3(SET),
+		 .pin_4(LEDK[3]),
+		 .pin_5(LEDK[2]),
+		 .pin_6(LEDK[1])
+	);
+
+endmodule