FreeCalypso > hg > fc-small-hw

diff lunalcd2/src/vsrc/current_select.v @ 59:d5d14b426faa

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents
children
line wrap: on
line diff
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/current_select.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,23 @@
+module current_select (Vio, SET);
+
+input Vio;
+output SET;
+
+wire sw_1mA, sw_2mA, sw_4mA, sw_8mA;
+
+pkg_DIP_SW_x4 dipsw (	.pin_1(Vio),
+			.pin_2(sw_8mA),
+			.pin_3(Vio),
+			.pin_4(sw_4mA),
+			.pin_5(Vio),
+			.pin_6(sw_2mA),
+			.pin_7(Vio),
+			.pin_8(sw_1mA)
+	);
+
+resistor R_1mA (sw_1mA, SET);
+resistor R_2mA (sw_2mA, SET);
+resistor R_4mA (sw_4mA, SET);
+resistor R_8mA (sw_8mA, SET);
+
+endmodule