diff lunalcd2/src/vsrc/lcd_module.v @ 59:d5d14b426faa

lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents
children
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd2/src/vsrc/lcd_module.v	Fri Jun 25 18:44:11 2021 +0000
@@ -0,0 +1,50 @@
+module lcd_module (GND, VCI, IOVCC, DB, RD, WR, RS, CS, RESET, IM0, LEDA, LEDK);
+
+input GND, VCI, IOVCC;
+inout [15:0] DB;
+input RD, WR, RS, CS, RESET, IM0;
+input LEDA;
+input [1:3] LEDK;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+lcd_module_fp pkg (.pin_1(DB[15]),
+		   .pin_2(DB[14]),
+		   .pin_3(DB[13]),
+		   .pin_4(DB[12]),
+		   .pin_5(DB[11]),
+		   .pin_6(DB[10]),
+		   .pin_7(DB[9]),
+		   .pin_8(DB[8]),
+		   .pin_9(GND),
+		   .pin_10(DB[7]),
+		   .pin_11(DB[6]),
+		   .pin_12(DB[5]),
+		   .pin_13(DB[4]),
+		   .pin_14(DB[3]),
+		   .pin_15(DB[2]),
+		   .pin_16(DB[1]),
+		   .pin_17(DB[0]),
+		   .pin_18(IOVCC),
+		   .pin_19(VCI),
+		   .pin_20(RD),
+		   .pin_21(WR),
+		   .pin_22(RS),
+		   .pin_23(CS),
+		   .pin_24(RESET),
+		   .pin_25(IM0),
+		   .pin_26(GND),
+		   .pin_27(LEDA),
+		   .pin_28(LEDK[1]),
+		   .pin_29(LEDK[2]),
+		   .pin_30(LEDK[3]),
+		   /* the remaining pins are NC */
+		   .pin_31(),
+		   .pin_32(),
+		   .pin_33(),
+		   .pin_34(),
+		   .pin_35(),
+		   .pin_36()
+	);
+
+endmodule