FreeCalypso DUART28 Adapter
Board design specification

1. What it is and why it is desired

Under our FreeCalypso umbrella we have a family of hardware products based on
the Calypso chipset from Texas Instruments.  The Calypso chip has two UARTs,
one with TxD & RxD data leads plus RTS & CTS flow control, and the other with
TxD & RxD data leads only.  There is also a convention whereby some Calypso
GPIOs are defined to be additional modem control signals and associated with
the Modem UART (the one that has RTS & CTS flow control in addition to
TxD & RxD), thus the result is one UART with a near-complete set of modem
control signals and one UART with data leads only.

The convention established in FreeCalypso is that all of our Calypso development
boards bring out both Calypso UARTs in their native form, which is 2.8V native
logic levels, tolerant of 3.3V but not any higher voltages.  In order to connect
these UARTs to a PC or laptop serving as the development host, a separate USB
to low-voltage UART adapter board is used, preferably one that puts both UARTs
(two ttyUSBx devices) behind a single USB device.  Our USB to dual UART
converter chip of choice is FT2232D; this chip has been chosen over various
competitors because it provides two UART channels (ttyUSBx devices) in one USB
device, because it supports non-standard serial baud rates on both channels,
allowing us to use GSM-specific high baud rates of 203125, 406250 and 812500
bps, and because it supports the full set of modem control signals like one
would find on an old-fashioned RS-232 port.

Since we got our first FCDEV3B boards built in 2017 and up until the present,
we've been using FT2232D breakout boards made by PLDkit as our USB to dual UART
adapter:

http://pldkit.com/other/ft2232d-module

These generic FT2232D adapters work quite well for our current purposes, but
now we have several reasons for desiring our own custom-built adapter to
replace them, detailed below.

1.1. Desire for custom interface pinout

In FreeCalypso we have the following convention: all FC hardware products that
bring out both Calypso UARTs do so by way of a single 10-pin (2x5) 2.54 mm
header in a fixed pinout given below.  This convention was started with
FCDEV3B, our first FC hw product, and is now being continued with MMTB1 and
Caramel2 boards.  Our standardized DUART header pinout is as follows:

Header pin	Calypso signal
1		GND
2		GND
3		TX_IRDA
4		TX_MODEM
5		RX_IRDA
6		RX_MODEM
7		GPIO2_DCD
8		RTS_MODEM
9		GPIO3_DTR
10		CTS_MODEM

Pins 7 and 9 were originally left unused (they are unconnected on FCDEV3B), but
they have been assigned as DCD and DTR (from the host's perspective) starting
with MMTB1.  Note that while DCD and DTR in the table above are named from the
host's perspective, all Calypso signals ending with _MODEM or _IRDA are from
the chip's perspective, i.e., the opposite.

When we use FT2232D breakout boards from PLDkit as our USB to DUART adapter, we
use a custom hand-made ribbon cable with crimp terminations: a 10-wire ribbon
is used, the full ribbon runs intact in the main body of the cable, but toward
the FT2232D adapter board the ribbon is split in two, with 7 wires going to the
A side of PLDkit's breakout board and with 3 wires going to the B side.  Each
of the two subribbons (both the 7-wire one and the 3-wire one) gets terminated
onto a 15-position female connector, with the two resulting 15-pin connectors
mating with the two 15-pin single-row headers located on the two sides of
PLDkit's breakout board.

This current solution is much better than manually connecting each wire
individually: with connectors being solid pieces rather than individual wires,
a setup can be very easily taken down and then put back together, which is
absolutely essential for our mode of usage.  But the downside of this approach
is that once our two 15-position female connectors mate with PLDkit's headers,
there is no way to make a separate connection to other signals which are not
covered by our basic 10-wire set.  This limitation is becoming problematic for
two reasons:

1) Our upcoming Caramel2 board will have the same 10-pin DUART header as FCDEV3B
and MMTB1 (with DCD & DTR present like on MMTB1), but it will also have an
additional RI modem control output on another Calypso GPIO accessible on the
general expansion interface header.  There is no room to squeeze this extra RI
signal into our standardized 10-pin DUART interface, but this extra signal is
rarely needed.  The compromise solution currently being pursued is that the
main 10-wire ribbon will connect all UART signals (both UARTs) with the
exception of RI, and those who need RI should be able to connect it with a
separate individual wire, connecting to the GPIO1 pin on the general expansion
interface header on the Caramel2 side.  But if we use PLDkit breakout boards
with our current ribbon cables with crimp terminations, there will be no way to
connect this extra RI wire to the FT2232D adapter board when the big 15-pin
connector blocks the entire header.

2) PLDkit's FT2232D breakout boards bring out USB 5V on one of their pins, and
this auxiliary 5V output is useful in some applications.  We have one upcoming
application where this auxiliary 5V will be used to exercise the Calypso+Iota
chipset's VCHG boot mode, also on the upcoming Caramel2 board - but we get into
the same problem of the PLDkit board header pin becoming inaccessible when our
crimp-terminated ribbon cables are used.

If we replace the generic PLDkit breakout with our own custom FreeCalypso USB
to dual UART adapter board, we can easily solve these problems by implementing
our own custom header pinouts.  The new DUART28 adapter board covered by the
present design spec will bring out 3 headers as follows:

* One 10-pin header carrying TxD, RxD, RTS, CTS, DTR and DCD for UART 0 and
just TxD & RxD for UART 1, in a pinout exactly matching our standardized
FreeCalypso DUART interface;

* One 3-pin header carrying UART 0 auxiliary modem control inputs DSR and RI,
plus a ground pin;

* One 2-pin header bringing out USB 5V and GND, for auxiliary uses.

1.2. 3.3V vs. 2.8V logic levels

Calypso I/O pins have native 2.8V logic levels, but they are specified as being
tolerant of 3.3V.  They do have internal clamping diodes to the Calypso chip's
2.8V V-IO rail, but their forward drop voltage is right around 0.5 V, thus if
external inputs are at 0.5 V above V-IO (practically meaning 3.3V inputs), no
significant current flows through these clamping diodes.

When we use a raw FT2232D breakout board as our USB to FreeCalypso DUART
adapter, we are connecting the FT2232D chip's 3.3V outputs directly to Calypso
inputs; this arrangement has been working well for us since 2017, but a more
proper 2.8V DUART adapter is desirable for a few reasons:

* When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for
Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO
regulator (the one that produces the 2.8V V-IO rail) switches into sleep mode,
which has much looser regulation than in the regular Active mode.  In this
condition external 3.3V can feed into the V-IO rail through pull-up resistors
and pull the rail itself a little higher than where the chipset's own regulators
would have it, which is certainly not desirable.  If UART inputs to the Calypso
board are driven with 2.8V logic levels rather than 3.3V, this problem is not
expected to occur.

* If we are going to build a custom FreeCalypso DUART adapter for other reasons,
it is only proper to make it 2.8V native rather than 3.3V - after all, our
adapter is highly specific to Calypso applications, not generic, and Calypso
has native 2.8V I/O.

* We have a competitor: Sysmocom folks use CP2105 adapters (mv-uart adapter
board and other integrated designs) instead of our FT2232D, and their
CP2105-based designs operate at native 2.8V logic levels, no 3.3V.  For
political reasons it is important to be no worse than the competition, giving
us one more reason to go for native 2.8V.

Because FT2232D I/O (unlike CP2105, FT232R and many other chips that aren't
suitable for other reasons) cannot go below 3.3V, making an FT2232D-based
adapter put out 2.8V logic levels requires inserting an extra level shifter
after FT2232D outputs - we shall use an LVC buffer for this purpose.

1.3. Partial power-down considerations

The following two corner cases need to be considered, as each can be a trouble
spot:

1) When the USB to DUART adapter is connected to a host computer and thus has
USB power present, but the connected Calypso device is in the switched-off
state in the Iota VRPC sense (a condition that occurs all the time in normal
operation, e.g., whenever you are running fc-loadtool and waiting to press the
PWON button on the board), current can flow from USB DUART adapter outputs into
powered-down Calypso chip inputs.  This current flow cannot be eliminated
without putting LVC or similar buffers on the Calypso board side, but we need
to be mindful of this current and we need to limit it.

2) When a Calypso device is connected to the USB DUART adapter, the Calypso
device is up and running (VRPC Active state), but there is no USB host
connected, current can flow from Calypso outputs into a powered-down FT2232D
(or other front-end chips) in the USB DUART adapter.  With our current raw
FT2232D-to-Calypso arrangement we have about 5.8 mA of current flowing per pin
under the described condition, which is way too much.

If we replace the generic FT2232D breakout with our own custom adapter board
design, we can solve the second partial power-down problem (the case of Calypso
on, but no USB host) by inserting LVC buffers in front of FT2232D inputs -
these LVC buffers are fully specified for partial power-down applications and
have very small Ioff leakage current.

2. Circuit design

2.1. FT2232D core section

Our FT2232D core section (basically everything from the USB connector to the
FT2232D chip's ADBUS and BDBUS interfaces) is based on PLDkit's generic FT2232D
module:

ftp://ftp.freecalypso.org/pub/USB/FTDI/FT2232D_module_B_schematics.pdf

This core section is essentially boilerplate in which we have zero desire for
innovation, hence we would like to copy it from a known-working design.  In
this project the section in question has been recaptured in our ueda language
based on the above schematic drawing.

2.2. UART outputs from the adapter

We have a total of 4 outputs: TxD, RTS, DTR and TxD2.  Because we wish to put
out 2.8V logic levels rather than 3.3V, each output needs to pass through an
LVC buffer; we use a 74LVC541A as our buffer IC.

There is also a series resistor inserted into each output after the LVC buffer;
the initial value to be populated on the first board build is 2.2 kOhm, to be
further tuned empirically.  The purpose of these series resistors is to limit
the current that will flow from our DUART28 adapter into the Calypso target
when the Calypso is powered down - see section 1.3.  In our current setup with
direct FT2232D to Calypso connection (no series resistors) this current has
been measured to be somewhere around 1.77 mA, and it appears to be limited by
the current sourcing ability of FT2232D drivers (1 mA per datasheet).  However,
our new LVC buffers have much stronger drivers, specified to both source and
sink up to 24 mA, thus series resistors become mandatory for proper operation
in this partial power-down scenario.

The value of these series resistors is a delicate tuning job: they need to be
large enough to limit current flow in the partial power-down scenario, but they
cannot be too large, or they will adversely affect serial communication.  Each
of these series resistors will form an RC circuit together with various
parasitic capacitances on the Calypso target side; larger R translates to a
larger RC time constant, resulting in slower signal rise and fall times,
adversely affecting serial communication at higher baud rates.

We have an existing Calypso development board produced by another company that
features old-fashioned RS-232 interfaces (classic DE9F connectors) and uses an
on-board RS-232 to LVTTL/LVCMOS converter; this board features 1 kOhm series
resistors in the same place as in our proposed design, and it works fine at
812500 baud.  If we populate the same 1 kOhm resistors, the undesirable current
in the partial power-down scenario will be 2.8 mA per pin, which is greater
than our current 1.77 mA; with our current plan of populating 2.2 kOhm resistors
the current will be 1.27 mA, and we are hoping that 812500 baud communication
will still work OK.

2.3. UART inputs to the adapter

We have a total of 6 inputs: RxD, CTS, DSR, DCD, RI and RxD2.  These inputs
need to pass through LVC buffers just like the outputs, but for a different
reason.  With inputs there is no need for voltage level translation, but the
need for LVC buffers arises because of partial power-down considerations - the
scenario when the Calypso board is fully up and running and is connected to the
DUART adapter, but there is no USB host connected - see section 1.3.  If
Calypso UART outputs are connected directly to FT2232D inputs without any
intermediate buffers, this condition is handled very poorly, with about 5.8 mA
of current flowing per pin, which is certainly not acceptable for a proper
design.

Insertion of an LVC buffer into each input signal path neatly solves this
problem: these buffers are specifically designed for partial power-down
applications and have very small Ioff leakage current - listed as 0.1 uA
typical or 10 uA maximum in the 74LVC541A datasheet.

One additional complication is that we also have to add explicit pull-up
resistors (to our local 2.8V rail) on each of our 6 inputs in front of the
buffer IC.  Many of our UART inputs may be legitimately left unconnected, and
these unconnected inputs should be sensed by our FT2232D USB UART as high.  If
we were connecting to FT2232D inputs directly, the FT2232D chip's internal
pull-ups would take care of this condition, but when we have a 74LVC541A buffer
in front of these FT2232D inputs, this buffer IC's own inputs must not be left
floating.

2.4. LVC buffer details

We shall use two LVC buffer ICs of the same type (74LVC541A), one for the 4
outputs, the other for the 6 inputs.  Each 74LVC541A is an octal buffer, thus
some slots in each IC remain unused; all unused slots will have their A inputs
tied to GND.  Both nOE1 and nOE2 on each buffer IC are also tied to GND,
resulting in all buffers being always enabled.

The 74LVC541A buffer for outputs will have its Vcc supply pin fed with 2.8V, as
required in order to produce 2.8V logic levels on outputs from the adapter.
However, the other 74LVC541A buffer for inputs will have its Vcc supply pin fed
with 3.3V, same as FT2232D VCCIOA and VCCIOB.

When the inputs coming from the connected Calypso target have 2.8V logic levels
and ultimately need to go to FT2232D receivers operating at 3.3V, a sort of
translation will have to happen somewhere, with a CMOS input structure operating
with a 3.3V supply being fed 2.8V inputs.  We can make this translation happen
in the FT2232D if we use an intermediate LVC buffer powered at 2.8V or no
intermediate buffer at all, or we can make this translation happen in the LVC
buffer if the latter is powered with the same 3.3V as the FT2232D I/O pins.
The second approach has been chosen because the behaviour of 74LVC541A under
these conditions is much better understood than the behaviour of FT2232D I/O
cells under the same, thanks to much better documentation being available for
74LVC541A than for that part of FT2232D.

Please note, however, that the pull-up resistors on inputs before input-serving
74LVC541A buffer will be wired to our local 2.8V rail, not to 3.3V, even though
the buffer IC will be powered with 3.3V.  This way all interface signals exist
strictly in the 2.8V domain and never get exposed to 3.3V in any form.

2.5. LDO regulators

Two LDO regulators will be implemented on our adapter board, both powered from
USB 5V: one producing 3.3V, the other producing 2.8V.  Our 3.3V LDO will power
FT2232D VCCIOA & VCCIOB and the input-serving 74LVC541A buffer, whereas the
other 2.8V LDO will power our output-serving 74LVC541A buffer and our input
pull-up resistors.  Both LDOs will be of TLV702 family from TI, based on our
recent good experiences with this LDO family in other projects.

The FT2232D chip's built-in 3.3V LDO won't be used: its 5 mA current limit
seems to be too small, and our current FT2232D adapter boards made by PLDkit
don't use it either, using an external beefier LDO instead.

3. PCB layout specification

3.1. Overall dimensions

The generic FT2232D breakout board from PLDkit which the present DUART28 seeks
to replace measures 39.37x46.99 mm or 1550x1850 mil.  If the present DUART28
circuit can be squeezed into the same size, great - but such squeeze is NOT
required.  If our DUART28 requires a larger PCB because of our greater circuit
complexity and having more components, using a larger PCB would be perfectly
fine - however much space is needed to get the job done.  There is no specific
form factor requirement, i.e., this project is a free-form design.

3.2. Layer count

PLDkit's FT2232D adapter board appears to have a 2-layer PCB, and our competitor
mv-uart by Sysmocom (CP2105-based) is known to have a 2-layer PCB thanks to
published design files.  However, we shall go by the same business logic as with
board dimensions: if the needed layout can be done in just 2 layers, great, but
if the PCB layout engineer feels that going to 4 layers would be better or would
make the layout job easier, it would be perfectly OK to have 4 layers.

3.3. Mounting holes

The PCB should have 4 mounting holes in the corners, accommodating M3 screws.
It is OK to increase overall board dimensions slightly to make room for these
mounting holes.

3.4. Placement of connectors

USB mini-B connector J1 must be placed along one of the board edges; it does not
matter along which edge, or exactly where.

Shrouded 2x5 header J2 can be placed anywhere, as long as the placement makes
sense for cable attachment purposes.  The cable plugged into this connector will
be a 10-wire ribbon terminated with an IDC connector, thus the body of the flat
cable will lie parallel to the board surface.  Orientation: the body of the
cable will face toward the even-numbered row of pins, i.e., away from the
polarizing tab identified with a silk screen mark in the currently drawn
footprint.

Little headers J3 and J4 can be placed anywhere; they are not shrouded and the
only things that can be connected to them are either individual jumper wires or
crimped assemblies with wires rising up, perpendicular to the board.

3.5. Connector silk screen labels

All three user connection headers J2, J3 and J4 shall have silk screen labels
identifying every pin.  J2 pins shall be labeled as follows, numbers in the
middle indicate physical pins and shall NOT be placed on the silk screen
themselves:

GND  1  2 GND
RxD2 3  4 RxD
TxD2 5  6 TxD
DCD  7  8 CTS
DTR  9 10 RTS

J3 pins shall be labeled as follows, numbers on the left indicate physical pins
and shall NOT be placed on the silk screen themselves:

1 GND
2 DSR
3 RI

J4 pins shall be labeled as follows, same deal with pin numbers:

1 +5V
2 GND

3.6. 74LVC541A slot assignment

74LVC541A is an octal buffer IC that can be seen as a bundle of 8 single buffers
with common output enables; the latter are always enabled in our present
circuit.  The present design uses two of these octal buffer ICs (see section
2.4): one with 4 signals and 4 unused slots (grounded A inputs, unconnected Y
outputs) and one with 6 signals and 2 unused slots.  The mapping of which signal
should go to which An/Yn slot is arbitrary from the standpoint of circuit
functionality, thus this mapping should be made at the time of PCB layout for
physical layout optimization.

The mapping of signals to U5 and U6 slots is defined in U5.slotmap and
U6.slotmap text files; to change these mappings, edit the two files to define
the desired mapping, then recompile the netlist by running 'make', producing an
updated pcb-netlist.txt generated file.

The preliminary slot mapping that exists in the present netlist was created as
a placeholder to pass compilation, and is NOT expected to be anywhere close to
optimal for layout!  Therefore, the PCB layout engineer is expected to review
this slot mapping and optimize it for layout.

3.7. Power bypass capacitors

By the very nature of power bypass capacitors, a netlist gives absolutely no
indication as to where they need to be placed - yet their physical placement is
essential to their circuit function.  Because the design of this board is
captured in ueda language instead of graphical schematics, it is possible that
the PCB layout engineer may have some difficulty with reading our ueda design
source to understand the design intent as to where each bypass capacitor should
be placed.  The following listing is intended to resolve this ambiguity:

* C4 and C7 need to be placed at the output of L1 on the P_5V net;
* C8 needs to be placed at the input of LDO regulator U3;
* C9 needs to be placed at the output of LDO regulator U3;
* C10 needs to be placed at the input of LDO regulator U4;
* C11 needs to be placed at the output of LDO regulator U4;
* C12 needs to be placed near pin 20 (Vcc) of U5;
* C13 needs to be placed near pin 20 (Vcc) of U6;
* C14 needs to be placed near pin 14 (VCCIOA) of U1;
* C15 needs to be placed near pin 31 (VCCIOB) of U1.