FreeCalypso > hg > fc-small-hw
view mmtb1/schem+bom/vsrc/interface.v @ 80:6bd0e0627938
sim-fpc-pasv: starting project with MCL
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 25 Oct 2022 03:17:34 +0000 |
parents | 0f9bdd60ce50 |
children |
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/* * This module encapsulates the FPC interface connector. */ module interface (GND, VBAT, PWON, nTESTRESET, Vio, TX_IRDA, RX_IRDA, TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, GPIO2_DCD, GPIO3_DTR, VSIM, SIM_IO, SIM_CLK, SIM_RST, EARP, EARN, MICP, MICN); input GND, VBAT, PWON, nTESTRESET; output Vio; input GPIO3_DTR, RX_MODEM, CTS_MODEM, RX_IRDA; output GPIO2_DCD, TX_MODEM, RTS_MODEM, TX_IRDA; output VSIM, SIM_CLK, SIM_RST; inout SIM_IO; output EARP, EARN; input MICP, MICN; /* instantiate the connector! */ conn_40pin_plus2 fpc_conn (.pin_1(VBAT), .pin_2(VBAT), .pin_3(VBAT), .pin_4(VBAT), .pin_5(VBAT), .pin_6(GND), .pin_7(GND), .pin_8(GND), .pin_9(GND), .pin_10(GND), .pin_11(TX_IRDA), .pin_12(RX_IRDA), .pin_13(Vio), .pin_14(), /* no connect to ADC */ .pin_15(PWON), .pin_16(), /* no connect to GPIO1 */ .pin_17(), /* no connect to GPIO0 */ .pin_18(TX_MODEM), .pin_19(RX_MODEM), .pin_20(RTS_MODEM), .pin_21(CTS_MODEM), .pin_22(GPIO3_DTR), .pin_23(GPIO2_DCD), .pin_24(Vio), /* SIM_CD to Vio per TI/OM/FC */ .pin_25(SIM_RST), .pin_26(SIM_IO), .pin_27(SIM_CLK), .pin_28(VSIM), .pin_29(GND), /* for SIM */ .pin_30(), /* no connect to Vbackup */ .pin_31(nTESTRESET), /* * Pins 32-40 differ between GTM900 and FCM40. * We connect EARP&EARN and MICP&MICN per GTM900 * and leave the rest unconnected on MMTB1. */ .pin_32(), .pin_33(), .pin_34(), .pin_35(EARP), .pin_36(EARN), .pin_37(MICP), .pin_38(MICN), .pin_39(), .pin_40(), /* ground the two mounting pads */ .pin_41(GND), .pin_42(GND) ); endmodule