module board ();

wire GND, P_5V, P_3V3, P_2V8;

wire [7:0] ADBUS, BDBUS;
wire [3:0] ACBUS, BCBUS;

USB_block usb ( .GND(GND),
		.P_5V(P_5V),
		.VCCIOA(P_3V3),
		.VCCIOB(P_3V3),
		.ADBUS(ADBUS),
		.ACBUS(ACBUS),
		.SI_WUA(P_3V3),
		.BDBUS(BDBUS),
		.BCBUS(BCBUS),
		.SI_WUB(P_3V3),
		.PWREN()	/* no connect */
	);

regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3));
regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8));

application_block app ( .GND(GND),
			.P_3V3(P_3V3),
			.P_2V8(P_2V8),
			.ADBUS(ADBUS),
			.ACBUS(ACBUS),
			.BDBUS(BDBUS)
	);

endmodule