module board ();

wire GND, P_5V, P_1V8, P_2V8;
wire REGEN;

wire OMAP_McBSP_DR, OMAP_McBSP_FS, OMAP_McBSP_CLK, OMAP_McBSP_DX;
wire OMAP_UART_RTS, OMAP_UART_RxD, OMAP_UART_TxD, OMAP_UART_CTS;

wire Calypso_MCSI_TXD, Calypso_MCSI_RXD, Calypso_MCSI_CLK, Calypso_MCSI_FSYNCH;
wire Calypso_UART_TxD, Calypso_UART_RxD, Calypso_UART_RTS, Calypso_UART_CTS;

conn_28pin bb_xm_conn ( .pin_1(P_1V8),
			.pin_2(P_5V),
			.pin_3(),
			.pin_4(OMAP_UART_CTS),
			.pin_5(),
			.pin_6(OMAP_UART_TxD),
			.pin_7(),
			.pin_8(OMAP_UART_RxD),
			.pin_9(),
			.pin_10(OMAP_UART_RTS),
			.pin_11(),
			.pin_12(OMAP_McBSP_DX),
			.pin_13(),
			.pin_14(OMAP_McBSP_CLK),
			.pin_15(),
			.pin_16(OMAP_McBSP_FS),
			.pin_17(),
			.pin_18(OMAP_McBSP_DR),
			.pin_19(),
			.pin_20(),
			.pin_21(),
			.pin_22(),
			.pin_23(),
			.pin_24(),
			.pin_25(REGEN),
			.pin_26(),
			.pin_27(GND),
			.pin_28(GND)
	);

capacitor C1 (P_5V, GND);
capacitor C3 (P_1V8, GND);

regulator reg ( .IN(P_5V),
		.OUT(P_2V8),
		.GND(GND),
		.EN(P_5V)
	);

capacitor C2 (P_2V8, GND);

/* U1 for MCSI */

buffer_ic_common U1common (.VccA(P_2V8),
			   .VccB(P_1V8),
			   .GND(GND),
			   .OE(GND)
	);

capacitor C4 (P_2V8, GND);
capacitor C5 (P_1V8, GND);

buffer_ic_slot U1slot1 (.A(Calypso_MCSI_TXD),
			.B(OMAP_McBSP_DR),
			.DIR(P_2V8)
	);

buffer_ic_slot U1slot2 (.A(Calypso_MCSI_FSYNCH),
			.B(OMAP_McBSP_FS),
			.DIR(P_2V8)
	);

buffer_ic_slot U1slot3 (.A(Calypso_MCSI_CLK),
			.B(OMAP_McBSP_CLK),
			.DIR(P_2V8)
	);

buffer_ic_slot U1slot4 (.A(Calypso_MCSI_RXD),
			.B(OMAP_McBSP_DX),
			.DIR(GND)
	);

header_5pin J2 (.pin_1(GND),
		.pin_2(Calypso_MCSI_TXD),
		.pin_3(Calypso_MCSI_FSYNCH),
		.pin_4(Calypso_MCSI_CLK),
		.pin_5(Calypso_MCSI_RXD)
	);

/* U2 for UART */

buffer_ic_common U2common (.VccA(P_2V8),
			   .VccB(P_1V8),
			   .GND(GND),
			   .OE(GND)
	);

capacitor C6 (P_2V8, GND);
capacitor C7 (P_1V8, GND);

buffer_ic_slot U2slot1 (.A(Calypso_UART_CTS),
			.B(OMAP_UART_RTS),
			.DIR(GND)
	);

buffer_ic_slot U2slot2 (.A(Calypso_UART_TxD),
			.B(OMAP_UART_RxD),
			.DIR(P_2V8)
	);

buffer_ic_slot U2slot3 (.A(Calypso_UART_RxD),
			.B(OMAP_UART_TxD),
			.DIR(GND)
	);

buffer_ic_slot U2slot4 (.A(Calypso_UART_RTS),
			.B(OMAP_UART_CTS),
			.DIR(P_2V8)
	);

header_5pin J3 (.pin_1(GND),
		.pin_2(Calypso_UART_CTS),
		.pin_3(Calypso_UART_TxD),
		.pin_4(Calypso_UART_RxD),
		.pin_5(Calypso_UART_RTS)
	);

endmodule