FreeCalypso > hg > fc-small-hw
view fc-uja/schem+bom/vsrc/application_block.v @ 82:803667312307
sim-fpc-pasv: schem+BOM design complete
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 25 Oct 2022 06:13:01 +0000 |
parents | 0f9bdd60ce50 |
children |
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/* * This module encapsulates the application function of our board: * going from FT2232D to target interfaces. */ module application_block (GND, P_3V3, P_2V8, ADBUS, ACBUS, BDBUS); input GND, P_3V3, P_2V8; inout [7:0] ADBUS, BDBUS; inout [3:0] ACBUS; /* target interface wires */ wire JTAG_TCK, JTAG_TDI, JTAG_TDO, JTAG_TMS; wire nTESTRESET; wire UART_TxD, UART_RxD; target_if target_if ( .GND(GND), .JTAG_TCK(JTAG_TCK), .JTAG_TDI(JTAG_TDI), .JTAG_TDO(JTAG_TDO), .JTAG_TMS(JTAG_TMS), .nTESTRESET(nTESTRESET), .nEMU[0](ACBUS[2]), .nEMU[1](ACBUS[3]), .UART_TxD(UART_TxD), .UART_RxD(UART_RxD) ); /* output buffers */ buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND)); capacitor output_buf_bypass_cap (P_2V8, GND); buffer_ic_slot buf_JTAG_TCK (.A(ADBUS[0]), .Y(JTAG_TCK), .nOE(ADBUS[5])); buffer_ic_slot buf_JTAG_TDI (.A(ADBUS[1]), .Y(JTAG_TDI), .nOE(ADBUS[5])); buffer_ic_slot buf_JTAG_TMS (.A(ADBUS[3]), .Y(JTAG_TMS), .nOE(ADBUS[5])); buffer_ic_slot buf_UART_TxD (.A(BDBUS[0]), .Y(UART_TxD), .nOE(GND)); /* input buffers */ buffer_ic_common input_buf_common (.Vcc(P_3V3), .GND(GND)); capacitor input_buf_bypass_cap (P_3V3, GND); buffer_ic_slot buf_JTAG_TDO (.A(JTAG_TDO), .Y(ADBUS[2]), .nOE(ADBUS[6])); buffer_ic_slot buf_UART_RxD (.A(UART_RxD), .Y(BDBUS[1]), .nOE(GND)); /* input pull-up resistors */ resistor JTAG_TDO_pullup (JTAG_TDO, P_2V8); resistor UART_RxD_pullup (UART_RxD, P_2V8); /* reset signal driver */ od_buffer reset_driver (.GND(GND), .Vcc(P_3V3), .A(ADBUS[7]), .Y(nTESTRESET)); capacitor reset_driver_bypass_cap (P_3V3, GND); /* pull-up resistors on control lines */ resistor ADBUS5_pullup (ADBUS[5], P_3V3); resistor ADBUS6_pullup (ADBUS[6], P_3V3); resistor ADBUS7_pullup (ADBUS[7], P_3V3); endmodule