view fc-uja/schem+bom/vsrc/regulator_ic.v @ 82:803667312307

sim-fpc-pasv: schem+BOM design complete
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 25 Oct 2022 06:13:01 +0000
parents 0f9bdd60ce50
children
line wrap: on
line source

module regulator_ic (IN, OUT, GND, EN);

input IN, GND, EN;
output OUT;

pkg_5pin pkg (  .pin_1(IN),
		.pin_2(GND),
		.pin_3(EN),
		.pin_4(),	/* no connect */
		.pin_5(OUT)
	);

endmodule