view duart28/src/primitives @ 35:846ebd21db8e

duart28/design-spec: minor fixes in the so-far-written section
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 14 Jul 2020 19:01:29 +0000
parents bd7eec55ebc0
children
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/*
 * This file defines the primitives to be instantiated from the structural
 * Verilog source for the board: IC package types, basic components and
 * subpackages to be mapped later in the MCL binding step.
 */

resistor	numpins 2;
capacitor	numpins 2;
inductor	numpins 2;

/* IC packages */
pkg_LQFP48	numpins 48;
pkg_5pin	numpins 5;
pkg_8pin	numpins 8;

/* 74LVC541A single buffer and common part subpackages */
buffer_ic_slot		mapped_pins (A, Y);
buffer_ic_common	mapped_pins (Vcc, GND, nOE1, nOE2);

/* crystal resonator */
xtal_2pin_pkg	numpins 2;

/* connectors */
header_2pin		numpins 2;
header_3pin		numpins 3;
header_10pin		numpins 10;
conn_miniUSB_plus4	numpins 9;