view duart28/src/vsrc/regulator_with_caps.v @ 67:a1d59c66a410

lunalcd2/pcb: add Makefile
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 23:08:00 +0000
parents 22aba3a61a4b
children
line wrap: on
line source

module regulator_with_caps (GND, IN, OUT);

input GND, IN;
output OUT;

regulator_ic reg (.IN(IN),
		  .OUT(OUT),
		  .GND(GND),
		  .EN(IN)
	);

capacitor input_cap (IN, GND);
capacitor output_cap (OUT, GND);

endmodule