view duart28/src/vsrc/target_if.v @ 29:ccb544045646

duart28: U5 & U6 preliminary slotmaps
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 29 Jun 2020 03:15:08 +0000
parents 22aba3a61a4b
children
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/* This module captures our target interfaces. */

module target_if (GND, UART0_TxD, UART0_RxD, UART0_RTS, UART0_CTS,
		  UART0_DTR, UART0_DSR, UART0_DCD, UART0_RI,
		  UART1_TxD, UART1_RxD);

input GND;

input UART0_TxD, UART0_RTS, UART0_DTR;
output UART0_RxD, UART0_CTS, UART0_DSR, UART0_DCD, UART0_RI;

input UART1_TxD;
output UART1_RxD;

/* main DUART signal set header */

header_10pin main_if (  .pin_1(GND),
			.pin_2(GND),
			.pin_3(UART1_RxD),
			.pin_4(UART0_RxD),
			.pin_5(UART1_TxD),
			.pin_6(UART0_TxD),
			.pin_7(UART0_DCD),
			.pin_8(UART0_CTS),
			.pin_9(UART0_DTR),
			.pin_10(UART0_RTS)
	);

/* auxiliary DSR and RI */

header_3pin aux_if (.pin_1(GND),
		    .pin_2(UART0_DSR),
		    .pin_3(UART0_RI)
	);

endmodule