view lunalcd2/src/Makefile @ 59:d5d14b426faa

lunalcd2: structural Verilog source captured
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 25 Jun 2021 18:44:11 +0000
parents
children 38c713964bb7
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VSRCS=	vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \
	vsrc/current_select.v vsrc/lcd_module.v
NETS=	sverp.unet

all:	${NETS}

sverp.unet:	${VSRCS} primitives Makefile
	ueda-sverp -o $@ ${VSRCS}

clean:
	rm -f *.unet *.txt *.csv errs elements.pcb