/*
 * This Verilog module encapsulates the header connector on which
 * the two Calypso UARTs will be brought out.
 */

module uart_bringout (GND, TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM,
		      GPIO_DCD, GPIO_DTR, TX_IRDA, RX_IRDA);

input GND;

input TX_MODEM, RTS_MODEM, TX_IRDA, GPIO_DCD;
output RX_MODEM, CTS_MODEM, RX_IRDA, GPIO_DTR;

header_10pin uart_header (.pin_1(GND),
			  .pin_2(GND),
			  .pin_3(TX_IRDA),
			  .pin_4(TX_MODEM),
			  .pin_5(RX_IRDA),
			  .pin_6(RX_MODEM),
			  .pin_7(GPIO_DCD),
			  .pin_8(RTS_MODEM),
			  .pin_9(GPIO_DTR),
			  .pin_10(CTS_MODEM)
	);

endmodule